Lines Matching full:indirect
99 int inst_idx, bool indirect);
513 * @indirect: indirectly write sram
518 bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode() argument
530 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
534 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
538 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
540 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
543 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
545 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
547 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
553 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
556 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
560 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
563 if (!indirect) in vcn_v4_0_3_mc_resume_dpg_mode()
565 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
568 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
571 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
574 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
577 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
579 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
582 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
584 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
586 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
589 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
595 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
599 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
601 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
603 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
608 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
611 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
613 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
616 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
620 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
622 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
724 * @indirect: indirectly write sram
730 uint8_t indirect) in vcn_v4_0_3_disable_clock_gating_dpg_mode() argument
757 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
761 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
765 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
769 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v4_0_3_disable_clock_gating_dpg_mode()
828 * @indirect: indirectly write sram
833 bool indirect) in vcn_v4_0_3_start_dpg_mode() argument
853 if (indirect) { in vcn_v4_0_3_start_dpg_mode()
864 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
872 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
876 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
888 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
892 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
899 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
906 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
912 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v4_0_3_start_dpg_mode()
914 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); in vcn_v4_0_3_start_dpg_mode()
919 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
924 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
926 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); in vcn_v4_0_3_start_dpg_mode()
931 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
933 if (indirect) in vcn_v4_0_3_start_dpg_mode()
2049 int inst_idx, bool indirect) in vcn_v4_0_3_enable_ras() argument
2062 tmp, 0, indirect); in vcn_v4_0_3_enable_ras()
2067 tmp, 0, indirect); in vcn_v4_0_3_enable_ras()
2072 tmp, 0, indirect); in vcn_v4_0_3_enable_ras()