516  * @indirect: indirectly write sram
521 					bool indirect)  in vcn_v4_0_mc_resume_dpg_mode()  argument
532 		if (!indirect) {  in vcn_v4_0_mc_resume_dpg_mode()
535 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
538 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
540 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
543 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
545 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
547 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
553 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
556 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
560 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
563 	if (!indirect)  in vcn_v4_0_mc_resume_dpg_mode()
565 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
568 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
571 	if (!indirect) {  in vcn_v4_0_mc_resume_dpg_mode()
574 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
577 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
579 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
582 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
584 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
586 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
589 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
594 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
597 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
599 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
601 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
606 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
609 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
611 			VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
614 			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
619 			adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
861  * @indirect: indirectly write sram
867 						   uint8_t indirect)  in vcn_v4_0_disable_clock_gating_dpg_mode()  argument
900 		VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
904 		VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
908 		VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
912 		VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
976 				bool indirect)  in vcn_v4_0_enable_ras()  argument
991 			      tmp, 0, indirect);  in vcn_v4_0_enable_ras()
996 			      tmp, 0, indirect);  in vcn_v4_0_enable_ras()
1003  * @indirect: indirectly write sram
1007 static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)  in vcn_v4_0_start_dpg_mode()  argument
1024 	if (indirect)  in vcn_v4_0_start_dpg_mode()
1028 	vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1034 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1038 		VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1050 		VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1054 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1061 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
1068 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
1074 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
1076 	vcn_v4_0_mc_resume_dpg_mode(vinst, indirect);  in vcn_v4_0_start_dpg_mode()
1081 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1086 		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1088 	vcn_v4_0_enable_ras(vinst, indirect);  in vcn_v4_0_start_dpg_mode()
1093 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1096 	if (indirect)  in vcn_v4_0_start_dpg_mode()