Lines Matching +full:1 +full:x
53 # define AUTO_INCREMENT_IND_0 (1 << 0)
66 # define RST_REG (1 << 0)
68 # define CK_DISABLE (1 << 0)
69 # define CKEN (1 << 24)
72 #define VGA_MEMORY_DISABLE (1 << 4)
75 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
78 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
83 #define SPLL_RESET (1 << 0)
84 #define SPLL_SLEEP (1 << 1)
85 #define SPLL_BYPASS_EN (1 << 3)
86 #define SPLL_REF_DIV(x) ((x) << 4) argument
88 #define SPLL_PDIV_A(x) ((x) << 20) argument
92 #define SCLK_MUX_SEL(x) ((x) << 0) argument
94 #define SPLL_CTLREQ_CHG (1 << 23)
95 #define SCLK_MUX_UPDATE (1 << 26)
97 #define SPLL_FB_DIV(x) ((x) << 0) argument
100 #define SPLL_DITHEN (1 << 28)
104 #define SPLL_CHG_STATUS (1 << 1)
106 #define SPLL_SW_DIR_CONTROL (1 << 0)
107 # define SPLL_REFCLK_SEL(x) ((x) << 26) argument
111 #define SSEN (1 << 0)
112 #define CLK_S(x) ((x) << 4) argument
116 #define CLK_V(x) ((x) << 0) argument
121 # define AUTOSCALE_ON_SS_CLEAR (1 << 9)
134 # define UPLL_PDIV_A(x) ((x) << 0) argument
136 # define UPLL_PDIV_B(x) ((x) << 8) argument
138 # define VCLK_SRC_SEL(x) ((x) << 20) argument
140 # define DCLK_SRC_SEL(x) ((x) << 25) argument
143 # define UPLL_FB_DIV(x) ((x) << 0) argument
153 # define MPLL_CLKOUT_SEL(x) ((x) << 8) argument
157 # define XTALIN_DIVIDE (1 << 1)
158 # define BCLK_AS_XCLK (1 << 2)
160 # define FORCE_BIF_REFCLK_EN (1 << 3)
161 # define MUX_TCLK_TO_XCLK (1 << 8)
164 # define CMON_CLK_SEL(x) ((x) << 0) argument
166 # define TMON_CLK_SEL(x) ((x) << 8) argument
169 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) argument
171 # define ZCLK_SEL(x) ((x) << 8) argument
175 #define DPM_EVENT_SRC(x) ((x) << 0) argument
177 #define DIG_THERM_DPM(x) ((x) << 14) argument
181 #define FDO_PWM_DUTY(x) ((x) << 9) argument
185 #define DIG_THERM_INTH(x) ((x) << 8) argument
188 #define DIG_THERM_INTL(x) ((x) << 16) argument
191 #define THERM_INT_MASK_HIGH (1 << 24)
192 #define THERM_INT_MASK_LOW (1 << 25)
195 #define TEMP_SEL(x) ((x) << 20) argument
199 #define ASIC_MAX_TEMP(x) ((x) << 0) argument
202 #define CTF_TEMP(x) ((x) << 9) argument
207 #define FDO_STATIC_DUTY(x) ((x) << 0) argument
211 #define FMAX_DUTY100(x) ((x) << 0) argument
215 #define TMIN(x) ((x) << 0) argument
218 #define FDO_PWM_MODE(x) ((x) << 11) argument
221 #define TACH_PWM_RESP_RATE(x) ((x) << 25) argument
226 # define EDGE_PER_REV(x) ((x) << 0) argument
229 # define TARGET_PERIOD(x) ((x) << 3) argument
233 # define TACH_PERIOD(x) ((x) << 0) argument
238 # define GLOBAL_PWRMGT_EN (1 << 0)
239 # define STATIC_PM_EN (1 << 1)
240 # define THERMAL_PROTECTION_DIS (1 << 2)
241 # define THERMAL_PROTECTION_TYPE (1 << 3)
242 # define SW_SMIO_INDEX(x) ((x) << 6) argument
243 # define SW_SMIO_INDEX_MASK (1 << 6)
245 # define VOLT_PWRMGT_EN (1 << 10)
246 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
249 # define SCLK_PWRMGT_OFF (1 << 0)
250 # define SCLK_LOW_D1 (1 << 1)
251 # define FIR_RESET (1 << 4)
252 # define FIR_FORCE_TREND_SEL (1 << 5)
253 # define FIR_TREND_MODE (1 << 6)
254 # define DYN_GFX_CLK_OFF_EN (1 << 7)
255 # define GFX_CLK_FORCE_ON (1 << 8)
256 # define GFX_CLK_REQUEST_OFF (1 << 9)
257 # define GFX_CLK_FORCE_OFF (1 << 10)
258 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
259 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
260 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
261 # define DYN_LIGHT_SLEEP_EN (1 << 14)
270 # define UTC_0(x) ((x) << 0) argument
272 # define DTC_0(x) ((x) << 10) argument
276 # define BSP(x) ((x) << 0) argument
278 # define BSU(x) ((x) << 16) argument
281 # define CG_R(x) ((x) << 0) argument
283 # define CG_L(x) ((x) << 16) argument
287 # define CG_GICST(x) ((x) << 0) argument
289 # define CG_GIPOT(x) ((x) << 16) argument
293 # define SST(x) ((x) << 0) argument
295 # define SSTU(x) ((x) << 16) argument
299 # define DISP1_GAP(x) ((x) << 0) argument
301 # define DISP2_GAP(x) ((x) << 2) argument
303 # define VBI_TIMER_COUNT(x) ((x) << 4) argument
305 # define VBI_TIMER_UNIT(x) ((x) << 20) argument
307 # define DISP1_GAP_MCHG(x) ((x) << 24) argument
309 # define DISP2_GAP_MCHG(x) ((x) << 26) argument
318 # define CAC_WINDOW(x) ((x) << 0) argument
326 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) argument
327 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
330 #define GRBM_RQ_PENDING (1 << 5)
331 #define VMC_BUSY (1 << 8)
332 #define MCB_BUSY (1 << 9)
333 #define MCB_NON_DISPLAY_BUSY (1 << 10)
334 #define MCC_BUSY (1 << 11)
335 #define MCD_BUSY (1 << 12)
336 #define SEM_BUSY (1 << 14)
337 #define IH_BUSY (1 << 17)
340 #define SOFT_RESET_BIF (1 << 1)
341 #define SOFT_RESET_DC (1 << 5)
342 #define SOFT_RESET_DMA1 (1 << 6)
343 #define SOFT_RESET_GRBM (1 << 8)
344 #define SOFT_RESET_HDP (1 << 9)
345 #define SOFT_RESET_IH (1 << 10)
346 #define SOFT_RESET_MC (1 << 11)
347 #define SOFT_RESET_ROM (1 << 14)
348 #define SOFT_RESET_SEM (1 << 15)
349 #define SOFT_RESET_VMC (1 << 17)
350 #define SOFT_RESET_DMA (1 << 20)
351 #define SOFT_RESET_TST (1 << 21)
352 #define SOFT_RESET_REGBB (1 << 22)
353 #define SOFT_RESET_ORB (1 << 23)
363 #define DMA_BUSY (1 << 5)
364 #define DMA1_BUSY (1 << 6)
367 #define ENABLE_L2_CACHE (1 << 0)
368 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
369 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) argument
370 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) argument
371 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
372 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
373 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) argument
374 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) argument
376 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
377 #define INVALIDATE_L2_CACHE (1 << 1)
378 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) argument
380 #define INVALIDATE_ONLY_PTE_CACHES 1
383 #define BANK_SELECT(x) ((x) << 0) argument
384 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) argument
385 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) argument
386 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
388 #define L2_BUSY (1 << 0)
390 #define ENABLE_CONTEXT (1 << 0)
391 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) argument
392 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
393 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
394 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
395 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
396 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
397 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
398 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
399 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
400 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
401 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
402 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
403 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
404 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) argument
422 * bit 1: pde0
429 #define MEMORY_CLIENT_RW_MASK (1 << 24)
455 #define MC_CG_ENABLE (1 << 18)
456 #define MC_LS_ENABLE (1 << 19)
472 #define ENABLE_L1_TLB (1 << 0)
473 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
475 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
479 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
505 #define CHANSIZE_OVERRIDE (1 << 11)
513 #define STATE0(x) ((x) << 0) argument
516 #define STATE1(x) ((x) << 5) argument
519 #define STATE2(x) ((x) << 10) argument
522 #define STATE3(x) ((x) << 15) argument
527 #define TRAIN_DONE_D0 (1 << 30)
528 #define TRAIN_DONE_D1 (1 << 31)
531 #define RUN_MASK (1 << 0)
536 #define MEM_FALL_OUT_CMD (1 << 8)
554 #define MC_SEQ_MISC0_REV_ID_VALUE 1
594 # define DLL_SPEED(x) ((x) << 0) argument
596 # define DLL_READY (1 << 6)
597 # define MC_INT_CNTL (1 << 7)
598 # define MRDCK0_PDNB (1 << 8)
599 # define MRDCK1_PDNB (1 << 9)
600 # define MRDCK0_RESET (1 << 16)
601 # define MRDCK1_RESET (1 << 17)
602 # define DLL_READY_READ (1 << 24)
604 # define MRDCK0_BYPASS (1 << 24)
605 # define MRDCK1_BYPASS (1 << 25)
608 # define MPLL_MCLK_SEL (1 << 11)
610 #define BWCTRL(x) ((x) << 20) argument
613 #define VCO_MODE(x) ((x) << 0) argument
615 #define CLKFRAC(x) ((x) << 4) argument
617 #define CLKF(x) ((x) << 16) argument
621 #define YCLK_POST_DIV(x) ((x) << 0) argument
624 #define YCLK_SEL(x) ((x) << 4) argument
625 #define YCLK_SEL_MASK (1 << 4)
628 #define CLKV(x) ((x) << 0) argument
631 #define CLKS(x) ((x) << 0) argument
635 #define CLOCK_GATING_DIS (1 << 23)
644 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
646 #define HDP_LS_ENABLE (1 << 0)
651 # define IH_RB_ENABLE (1 << 0)
652 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ argument
653 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
654 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
655 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ argument
656 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
657 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
661 # define RB_OVERFLOW (1 << 0)
666 # define ENABLE_INTR (1 << 0)
667 # define IH_MC_SWAP(x) ((x) << 1) argument
669 # define IH_MC_SWAP_16BIT 1
672 # define RPTR_REARM (1 << 4)
673 # define MC_WRREQ_CREDIT(x) ((x) << 15) argument
674 # define MC_WR_CLEAN_CNT(x) ((x) << 20) argument
675 # define MC_VMID(x) ((x) << 25) argument
680 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
681 # define IH_DUMMY_RD_EN (1 << 1)
682 # define IH_REQ_NONSNOOP_EN (1 << 3)
683 # define GEN_IH_INT_EN (1 << 8)
689 #define FB_READ_EN (1 << 0)
690 #define FB_WRITE_EN (1 << 1)
709 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) argument
711 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) argument
712 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) argument
713 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ argument
725 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) argument
726 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) argument
729 * x = legal delay value
733 # define HBR_CAPABLE (1 << 0) /* enabled by default */
736 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) argument
737 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) argument
739 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) argument
741 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) argument
743 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) argument
745 # define DESCRIPTION0(x) (((x) & 0xff) << 0) argument
746 # define DESCRIPTION1(x) (((x) & 0xff) << 8) argument
747 # define DESCRIPTION2(x) (((x) & 0xff) << 16) argument
748 # define DESCRIPTION3(x) (((x) & 0xff) << 24) argument
750 # define DESCRIPTION4(x) (((x) & 0xff) << 0) argument
751 # define DESCRIPTION5(x) (((x) & 0xff) << 8) argument
752 # define DESCRIPTION6(x) (((x) & 0xff) << 16) argument
753 # define DESCRIPTION7(x) (((x) & 0xff) << 24) argument
755 # define DESCRIPTION8(x) (((x) & 0xff) << 0) argument
756 # define DESCRIPTION9(x) (((x) & 0xff) << 8) argument
757 # define DESCRIPTION10(x) (((x) & 0xff) << 16) argument
758 # define DESCRIPTION11(x) (((x) & 0xff) << 24) argument
760 # define DESCRIPTION12(x) (((x) & 0xff) << 0) argument
761 # define DESCRIPTION13(x) (((x) & 0xff) << 8) argument
762 # define DESCRIPTION14(x) (((x) & 0xff) << 16) argument
763 # define DESCRIPTION15(x) (((x) & 0xff) << 24) argument
765 # define DESCRIPTION16(x) (((x) & 0xff) << 0) argument
766 # define DESCRIPTION17(x) (((x) & 0xff) << 8) argument
769 # define AUDIO_ENABLED (1 << 31)
776 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) argument
780 #define PRIORITY_OFF (1 << 16)
781 #define PRIORITY_ALWAYS_ON (1 << 20)
785 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) argument
787 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) argument
788 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) argument
792 # define VLINE_OCCURRED (1 << 0)
793 # define VLINE_ACK (1 << 4)
794 # define VLINE_STAT (1 << 12)
795 # define VLINE_INTERRUPT (1 << 16)
796 # define VLINE_INTERRUPT_TYPE (1 << 17)
799 # define VBLANK_OCCURRED (1 << 0)
800 # define VBLANK_ACK (1 << 4)
801 # define VBLANK_STAT (1 << 12)
802 # define VBLANK_INTERRUPT (1 << 16)
803 # define VBLANK_INTERRUPT_TYPE (1 << 17)
807 # define VBLANK_INT_MASK (1 << 0)
808 # define VLINE_INT_MASK (1 << 4)
811 # define LB_D1_VLINE_INTERRUPT (1 << 2)
812 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
813 # define DC_HPD1_INTERRUPT (1 << 17)
814 # define DC_HPD1_RX_INTERRUPT (1 << 18)
815 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
816 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
817 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
818 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
820 # define LB_D2_VLINE_INTERRUPT (1 << 2)
821 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
822 # define DC_HPD2_INTERRUPT (1 << 17)
823 # define DC_HPD2_RX_INTERRUPT (1 << 18)
824 # define DISP_TIMER_INTERRUPT (1 << 24)
826 # define LB_D3_VLINE_INTERRUPT (1 << 2)
827 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
828 # define DC_HPD3_INTERRUPT (1 << 17)
829 # define DC_HPD3_RX_INTERRUPT (1 << 18)
831 # define LB_D4_VLINE_INTERRUPT (1 << 2)
832 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
833 # define DC_HPD4_INTERRUPT (1 << 17)
834 # define DC_HPD4_RX_INTERRUPT (1 << 18)
836 # define LB_D5_VLINE_INTERRUPT (1 << 2)
837 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
838 # define DC_HPD5_INTERRUPT (1 << 17)
839 # define DC_HPD5_RX_INTERRUPT (1 << 18)
841 # define LB_D6_VLINE_INTERRUPT (1 << 2)
842 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
843 # define DC_HPD6_INTERRUPT (1 << 17)
844 # define DC_HPD6_RX_INTERRUPT (1 << 18)
848 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
849 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
852 # define GRPH_PFLIP_INT_MASK (1 << 0)
853 # define GRPH_PFLIP_INT_TYPE (1 << 8)
863 # define DC_HPDx_INT_STATUS (1 << 0)
864 # define DC_HPDx_SENSE (1 << 1)
865 # define DC_HPDx_RX_INT_STATUS (1 << 8)
873 # define DC_HPDx_INT_ACK (1 << 0)
874 # define DC_HPDx_INT_POLARITY (1 << 8)
875 # define DC_HPDx_INT_EN (1 << 16)
876 # define DC_HPDx_RX_INT_ACK (1 << 20)
877 # define DC_HPDx_RX_INT_EN (1 << 24)
885 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) argument
886 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) argument
887 # define DC_HPDx_EN (1 << 28)
890 # define STUTTER_ENABLE (1 << 0)
902 #define GRBM_READ_TIMEOUT(x) ((x) << 0) argument
905 #define RLC_RQ_PENDING (1 << 0)
906 #define RLC_BUSY (1 << 8)
907 #define TC_BUSY (1 << 9)
911 #define RING2_RQ_PENDING (1 << 4)
912 #define SRBM_RQ_PENDING (1 << 5)
913 #define RING1_RQ_PENDING (1 << 6)
914 #define CF_RQ_PENDING (1 << 7)
915 #define PF_RQ_PENDING (1 << 8)
916 #define GDS_DMA_RQ_PENDING (1 << 9)
917 #define GRBM_EE_BUSY (1 << 10)
918 #define DB_CLEAN (1 << 12)
919 #define CB_CLEAN (1 << 13)
920 #define TA_BUSY (1 << 14)
921 #define GDS_BUSY (1 << 15)
922 #define VGT_BUSY (1 << 17)
923 #define IA_BUSY_NO_DMA (1 << 18)
924 #define IA_BUSY (1 << 19)
925 #define SX_BUSY (1 << 20)
926 #define SPI_BUSY (1 << 22)
927 #define BCI_BUSY (1 << 23)
928 #define SC_BUSY (1 << 24)
929 #define PA_BUSY (1 << 25)
930 #define DB_BUSY (1 << 26)
931 #define CP_COHERENCY_BUSY (1 << 28)
932 #define CP_BUSY (1 << 29)
933 #define CB_BUSY (1 << 30)
934 #define GUI_ACTIVE (1 << 31)
937 #define SE_DB_CLEAN (1 << 1)
938 #define SE_CB_CLEAN (1 << 2)
939 #define SE_BCI_BUSY (1 << 22)
940 #define SE_VGT_BUSY (1 << 23)
941 #define SE_PA_BUSY (1 << 24)
942 #define SE_TA_BUSY (1 << 25)
943 #define SE_SX_BUSY (1 << 26)
944 #define SE_SPI_BUSY (1 << 27)
945 #define SE_SC_BUSY (1 << 29)
946 #define SE_DB_BUSY (1 << 30)
947 #define SE_CB_BUSY (1 << 31)
950 # define RDERR_INT_ENABLE (1 << 0)
951 # define GUI_IDLE_INT_ENABLE (1 << 19)
971 #define CP_CE_HALT (1 << 24)
972 #define CP_PFP_HALT (1 << 26)
973 #define CP_ME_HALT (1 << 28)
983 #define ROQ_IB1_START(x) ((x) << 0) argument
984 #define ROQ_IB2_START(x) ((x) << 8) argument
986 #define MEQ1_START(x) ((x) << 0) argument
987 #define MEQ2_START(x) ((x) << 8) argument
1011 #define CLIP_VTX_REORDER_ENA (1 << 0)
1012 #define NUM_CLIP_SEQ(x) ((x) << 1) argument
1019 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) argument
1020 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) argument
1023 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) argument
1024 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) argument
1025 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) argument
1026 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) argument
1035 #define MIN_POWER(x) ((x) << 0) argument
1038 #define MAX_POWER(x) ((x) << 16) argument
1042 #define MAX_POWER_DELTA(x) ((x) << 0) argument
1045 #define STI_SIZE(x) ((x) << 16) argument
1048 #define LTI_RATIO(x) ((x) << 27) argument
1062 #define VTX_DONE_DELAY(x) ((x) << 0) argument
1063 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1070 #define OVERRIDE (1 << 21)
1071 #define LS_OVERRIDE (1 << 22)
1078 #define BACKEND_DISABLE(x) ((x) << 16) argument
1080 #define NUM_PIPES(x) ((x) << 0) argument
1083 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
1086 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
1089 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
1092 #define NUM_GPUS(x) ((x) << 20) argument
1095 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) argument
1098 #define ROW_SIZE(x) ((x) << 28) argument
1118 #define RB_BUFSZ(x) ((x) << 0) argument
1119 #define RB_BLKSZ(x) ((x) << 8) argument
1121 #define RB_NO_UPDATE (1 << 27)
1122 #define RB_RPTR_WR_ENA (1 << 31)
1150 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1151 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1152 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1153 # define TIME_STAMP_INT_ENABLE (1 << 26)
1154 # define CP_RINGID2_INT_ENABLE (1 << 29)
1155 # define CP_RINGID1_INT_ENABLE (1 << 30)
1156 # define CP_RINGID0_INT_ENABLE (1 << 31)
1160 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
1161 # define TIME_STAMP_INT_STAT (1 << 26)
1162 # define CP_RINGID2_INT_STAT (1 << 29)
1163 # define CP_RINGID1_INT_STAT (1 << 30)
1164 # define CP_RINGID0_INT_STAT (1 << 31)
1167 # define RB_XSEL2(x) ((x) << 4) argument
1169 # define RB_XSEL (1 << 6)
1170 # define RB_YSEL (1 << 7)
1171 # define PKR_MAP(x) ((x) << 8) argument
1172 # define PKR_XSEL(x) ((x) << 10) argument
1174 # define PKR_YSEL(x) ((x) << 12) argument
1176 # define SC_MAP(x) ((x) << 16) argument
1178 # define SC_XSEL(x) ((x) << 18) argument
1180 # define SC_YSEL(x) ((x) << 20) argument
1182 # define SE_MAP(x) ((x) << 24) argument
1183 # define SE_XSEL(x) ((x) << 26) argument
1185 # define SE_YSEL(x) ((x) << 28) argument
1190 # define LS2_EXIT_TIME(x) ((x) << 17) argument
1194 # define MULTI_PIF (1 << 25)
1196 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) argument
1199 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) argument
1202 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) argument
1206 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) argument
1209 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) argument
1212 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) argument
1217 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) argument
1220 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) argument
1223 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) argument
1227 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) argument
1230 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) argument
1233 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) argument
1246 # define SLV_MEM_LS_EN (1 << 16)
1247 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
1248 # define MST_MEM_LS_EN (1 << 18)
1249 # define REPLAY_MEM_LS_EN (1 << 19)
1251 # define LC_REVERSE_RCVR (1 << 0)
1252 # define LC_REVERSE_XMIT (1 << 1)
1259 # define P_IGNORE_EDB_ERR (1 << 6)
1263 # define LC_L0S_INACTIVITY(x) ((x) << 8) argument
1266 # define LC_L1_INACTIVITY(x) ((x) << 12) argument
1269 # define LC_PMI_TO_L1_DIS (1 << 16)
1270 # define LC_ASPM_TO_L1_DIS (1 << 24)
1275 # define LC_LINK_WIDTH_X1 1
1282 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1283 # define LC_RECONFIG_NOW (1 << 8)
1284 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1285 # define LC_RENEGOTIATE_EN (1 << 10)
1286 # define LC_SHORT_RECONFIG_EN (1 << 11)
1287 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1288 # define LC_UPCONFIGURE_DIS (1 << 13)
1289 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) argument
1293 # define LC_XMIT_N_FTS(x) ((x) << 0) argument
1296 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1299 # define LC_GEN2_EN_STRAP (1 << 0)
1300 # define LC_GEN3_EN_STRAP (1 << 1)
1301 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1304 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1305 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1306 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1307 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1308 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1311 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1313 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1314 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1315 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1316 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1317 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1320 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1321 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1324 # define LC_GO_TO_RECOVERY (1 << 30)
1326 # define LC_REDO_EQ (1 << 5)
1327 # define LC_SET_QUIESCE (1 << 13)
1340 # define DCM (1 << 0)
1341 # define CG_DT(x) ((x) << 2) argument
1343 # define CLK_OD(x) ((x) << 6) argument
1349 # define DYN_OR_EN (1 << 0)
1350 # define DYN_RR_EN (1 << 1)
1351 # define G_DIV_ID(x) ((x) << 2) argument
1371 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1376 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
1409 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
1411 * 1 - memory (sync - via GRBM)
1417 #define WR_ONE_ADDR (1 << 16)
1418 #define WR_CONFIRM (1 << 20)
1419 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
1421 * 1 - pfp
1429 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
1431 * 1 - <
1438 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
1440 * 1 - mem
1442 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
1444 * 1 - pfp
1449 /* 1. header
1457 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) argument
1459 * 1 - GDS
1461 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) argument
1463 * 1 - PFP
1465 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) argument
1467 * 1 - GDS
1470 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1472 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1473 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) argument
1475 * 1 - 8 in 16
1479 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) argument
1481 * 1 - 8 in 16
1485 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1487 * 1 - register
1489 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1491 * 1 - register
1493 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1494 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1495 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1498 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1499 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1500 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1501 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1502 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1503 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1504 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1505 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1506 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1507 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1508 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1509 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1510 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1511 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1512 # define PACKET3_TC_ACTION_ENA (1 << 23)
1513 # define PACKET3_CB_ACTION_ENA (1 << 25)
1514 # define PACKET3_DB_ACTION_ENA (1 << 26)
1515 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1516 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1518 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) argument
1521 #define EVENT_TYPE(x) ((x) << 0) argument
1522 #define EVENT_INDEX(x) ((x) << 8) argument
1524 * 1 - ZPASS_DONE
1532 #define INV_L2 (1 << 20)
1535 #define DATA_SEL(x) ((x) << 29) argument
1537 * 1 - send low 32bit data
1541 #define INT_SEL(x) ((x) << 24) argument
1543 * 1 - interrupt only (DATA_SEL = 0)
1588 # define DMA_RB_ENABLE (1 << 0)
1589 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ argument
1590 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1591 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1592 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1593 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ argument
1602 # define DMA_IB_ENABLE (1 << 0)
1603 # define DMA_IB_SWAP_ENABLE (1 << 4)
1604 # define CMD_VMID_FORCE (1 << 31)
1607 # define TRAP_ENABLE (1 << 0)
1608 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1609 # define SEM_WAIT_INT_ENABLE (1 << 2)
1610 # define DATA_SWAP_ENABLE (1 << 3)
1611 # define FENCE_SWAP_ENABLE (1 << 4)
1612 # define CTXEMPTY_INT_ENABLE (1 << 28)
1614 # define DMA_IDLE (1 << 0)
1618 # define MEM_POWER_OVERRIDE (1 << 8)
1622 # define PG_CNTL_ENABLE (1 << 0)
1637 (1 << 26) | \
1638 (1 << 21) | \
1655 #define VCE_CLK_EN (1 << 0)
1663 #define VCE_ECPU_SOFT_RESET (1 << 0)
1664 #define VCE_FME_SOFT_RESET (1 << 2)
1680 # define VCE_FW_REG_STATUS_BUSY (1 << 0)
1681 # define VCE_FW_REG_STATUS_PASS (1 << 3)
1682 # define VCE_FW_REG_STATUS_DONE (1 << 11)
1738 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
1743 #define EVERGREEN_CRTC_MASTER_EN (1 << 0)
1744 #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
1746 #define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
1747 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
1752 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
1760 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
1763 # define EVERGREEN_INTERLEAVE_EN (1 << 0)
1766 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
1778 #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
1783 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)
1784 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8)
1785 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
1786 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
1787 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
1788 # define AVIVO_DVGA_CONTROL_ROTATE (1 << 24)
1792 # define R600_BIOS_ROM_DIS (1 << 1)
1795 # define R600_SCK_OVERWRITE (1 << 1)
1800 #define FMT_TRUNCATE_EN (1 << 0)
1801 #define FMT_TRUNCATE_DEPTH (1 << 4)
1802 #define FMT_SPATIAL_DITHER_EN (1 << 8)
1803 #define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) argument
1804 #define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
1805 #define FMT_FRAME_RANDOM_ENABLE (1 << 13)
1806 #define FMT_RGB_RANDOM_ENABLE (1 << 14)
1807 #define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
1808 #define FMT_TEMPORAL_DITHER_EN (1 << 16)
1809 #define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
1810 #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) argument
1811 #define FMT_TEMPORAL_LEVEL (1 << 24)
1812 #define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1813 #define FMT_25FRC_SEL(x) ((x) << 26) argument
1814 #define FMT_50FRC_SEL(x) ((x) << 28) argument
1815 #define FMT_75FRC_SEL(x) ((x) << 30) argument
1831 #define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) argument
1833 #define EVERGREEN_GRPH_DEPTH_16BPP 1
1835 #define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) argument
1837 #define EVERGREEN_ADDR_SURF_4_BANK 1
1840 #define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) argument
1841 #define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) argument
1843 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1
1846 #define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) argument
1850 #define EVERGREEN_GRPH_FORMAT_ARGB565 1
1858 #define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
1865 #define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) argument
1867 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1
1870 #define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) argument
1872 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1
1878 #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) argument
1880 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
1883 #define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) argument
1885 #define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
1889 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
1894 #define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) argument
1896 # define EVERGREEN_GRPH_ENDIAN_8IN16 1
1899 #define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) argument
1901 # define EVERGREEN_GRPH_RED_SEL_G 1
1904 #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) argument
1906 # define EVERGREEN_GRPH_GREEN_SEL_B 1
1909 #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) argument
1911 # define EVERGREEN_GRPH_BLUE_SEL_A 1
1914 #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) argument
1916 # define EVERGREEN_GRPH_ALPHA_SEL_R 1
1928 #define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8)
1940 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
1941 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
1943 #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
1951 # define EVERGREEN_CURSOR_EN (1 << 0)
1952 # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) argument
1954 # define EVERGREEN_CURSOR_24_1 1
1957 # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)
1958 # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)
1959 # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) argument
1961 # define EVERGREEN_CURSOR_URGENT_1_8 1
1974 # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
1975 # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)
1976 # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)
1977 # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
1981 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) argument
1983 # define NI_INPUT_CSC_PROG_COEFF 1
1985 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) argument
1988 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) argument
1990 # define NI_OUTPUT_CSC_TV_RGB 1
1995 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) argument
1998 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) argument
2000 # define NI_DEGAMMA_SRGB_24 1
2002 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) argument
2003 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) argument
2004 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) argument
2007 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) argument
2009 # define NI_GAMUT_REMAP_PROG_COEFF 1
2012 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) argument
2015 # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) argument
2017 # define NI_REGAMMA_SRGB_24 1
2021 # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) argument
2025 # define NI_GRPH_PRESCALE_BYPASS (1 << 4)
2028 # define NI_OVL_PRESCALE_BYPASS (1 << 4)
2031 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) argument
2033 # define NI_INPUT_GAMMA_BYPASS 1
2036 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) argument
2043 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
2048 # define EVERGREEN_CRTC_MASTER_EN (1 << 0)
2049 # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
2051 # define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
2052 # define EVERGREEN_CRTC_V_BLANK (1 << 0)
2057 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
2065 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
2153 #define VCEPLL_PDIV_A(x) ((x) << 0) argument
2155 #define VCEPLL_PDIV_B(x) ((x) << 8) argument
2157 #define EVCLK_SRC_SEL(x) ((x) << 20) argument
2159 #define ECCLK_SRC_SEL(x) ((x) << 25) argument
2163 #define VCEPLL_FB_DIV(x) ((x) << 0) argument