Lines Matching +full:0 +full:x3e000000
35 #define SI_MAX_BACKENDS_MASK 0xFF
36 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
38 #define SI_MAX_SIMDS_MASK 0x0FFF
39 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
41 #define SI_MAX_PIPES_MASK 0xFF
42 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
43 #define SI_MAX_LDS_NUM 0xFFFF
45 #define SI_MAX_TCC_MASK 0xFFFF
49 #define SMC_IND_INDEX_0 0x80
50 #define SMC_IND_DATA_0 0x81
52 #define SMC_IND_ACCESS_CNTL 0x8A
53 # define AUTO_INCREMENT_IND_0 (1 << 0)
54 #define SMC_MESSAGE_0 0x8B
55 #define SMC_RESP_0 0x8C
58 #define SMC_CG_IND_START 0xc0030000
59 #define SMC_CG_IND_END 0xc0040000
61 #define CG_CGTT_LOCAL_0 0x400
62 #define CG_CGTT_LOCAL_1 0x401
65 #define SMC_SYSCON_RESET_CNTL 0x80000000
66 # define RST_REG (1 << 0)
67 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
68 # define CK_DISABLE (1 << 0)
71 #define VGA_HDP_CONTROL 0xCA
74 #define DCCG_DISP_SLOW_SELECT_REG 0x13F
75 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
76 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
77 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0
82 #define CG_SPLL_FUNC_CNTL 0x180
83 #define SPLL_RESET (1 << 0)
87 #define SPLL_REF_DIV_MASK (0x3f << 4)
89 #define SPLL_PDIV_A_MASK (0x7f << 20)
91 #define CG_SPLL_FUNC_CNTL_2 0x181
92 #define SCLK_MUX_SEL(x) ((x) << 0)
93 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
96 #define CG_SPLL_FUNC_CNTL_3 0x182
97 #define SPLL_FB_DIV(x) ((x) << 0)
98 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
99 #define SPLL_FB_DIV_SHIFT 0
101 #define CG_SPLL_FUNC_CNTL_4 0x183
103 #define SPLL_STATUS 0x185
105 #define SPLL_CNTL_MODE 0x186
106 #define SPLL_SW_DIR_CONTROL (1 << 0)
110 #define CG_SPLL_SPREAD_SPECTRUM 0x188
111 #define SSEN (1 << 0)
113 #define CLK_S_MASK (0xfff << 4)
115 #define CG_SPLL_SPREAD_SPECTRUM_2 0x189
116 #define CLK_V(x) ((x) << 0)
117 #define CLK_V_MASK (0x3ffffff << 0)
118 #define CLK_V_SHIFT 0
120 #define CG_SPLL_AUTOSCALE_CNTL 0x18b
124 #define CG_UPLL_FUNC_CNTL 0x18d
125 # define UPLL_RESET_MASK 0x00000001
126 # define UPLL_SLEEP_MASK 0x00000002
127 # define UPLL_BYPASS_EN_MASK 0x00000004
128 # define UPLL_CTLREQ_MASK 0x00000008
129 # define UPLL_VCO_MODE_MASK 0x00000600
130 # define UPLL_REF_DIV_MASK 0x003F0000
131 # define UPLL_CTLACK_MASK 0x40000000
132 # define UPLL_CTLACK2_MASK 0x80000000
133 #define CG_UPLL_FUNC_CNTL_2 0x18e
134 # define UPLL_PDIV_A(x) ((x) << 0)
135 # define UPLL_PDIV_A_MASK 0x0000007F
137 # define UPLL_PDIV_B_MASK 0x00007F00
139 # define VCLK_SRC_SEL_MASK 0x01F00000
141 # define DCLK_SRC_SEL_MASK 0x3E000000
142 #define CG_UPLL_FUNC_CNTL_3 0x18f
143 # define UPLL_FB_DIV(x) ((x) << 0)
144 # define UPLL_FB_DIV_MASK 0x01FFFFFF
145 #define CG_UPLL_FUNC_CNTL_4 0x191
146 # define UPLL_SPARE_ISPARE9 0x00020000
147 #define CG_UPLL_FUNC_CNTL_5 0x192
148 # define RESET_ANTI_MUX_MASK 0x00000200
149 #define CG_UPLL_SPREAD_SPECTRUM 0x194
150 # define SSEN_MASK 0x00000001
152 #define MPLL_BYPASSCLK_SEL 0x197
154 # define MPLL_CLKOUT_SEL_MASK 0xFF00
156 #define CG_CLKPIN_CNTL 0x198
159 #define CG_CLKPIN_CNTL_2 0x199
163 #define THM_CLK_CNTL 0x19b
164 # define CMON_CLK_SEL(x) ((x) << 0)
165 # define CMON_CLK_SEL_MASK 0xFF
167 # define TMON_CLK_SEL_MASK 0xFF00
168 #define MISC_CLK_CNTL 0x19c
169 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
170 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
172 # define ZCLK_SEL_MASK 0xFF00
174 #define CG_THERMAL_CTRL 0x1c0
175 #define DPM_EVENT_SRC(x) ((x) << 0)
176 #define DPM_EVENT_SRC_MASK (7 << 0)
178 #define DIG_THERM_DPM_MASK 0x003FC000
180 #define CG_THERMAL_STATUS 0x1c1
182 #define FDO_PWM_DUTY_MASK (0xff << 9)
184 #define CG_THERMAL_INT 0x1c2
186 #define DIG_THERM_INTH_MASK 0x0000FF00
189 #define DIG_THERM_INTL_MASK 0x00FF0000
194 #define CG_MULT_THERMAL_CTRL 0x1c4
196 #define TEMP_SEL_MASK (0xff << 20)
198 #define CG_MULT_THERMAL_STATUS 0x1c5
199 #define ASIC_MAX_TEMP(x) ((x) << 0)
200 #define ASIC_MAX_TEMP_MASK 0x000001ff
201 #define ASIC_MAX_TEMP_SHIFT 0
203 #define CTF_TEMP_MASK 0x0003fe00
206 #define CG_FDO_CTRL0 0x1d5
207 #define FDO_STATIC_DUTY(x) ((x) << 0)
208 #define FDO_STATIC_DUTY_MASK 0x000000FF
209 #define FDO_STATIC_DUTY_SHIFT 0
210 #define CG_FDO_CTRL1 0x1d6
211 #define FMAX_DUTY100(x) ((x) << 0)
212 #define FMAX_DUTY100_MASK 0x000000FF
213 #define FMAX_DUTY100_SHIFT 0
214 #define CG_FDO_CTRL2 0x1d7
215 #define TMIN(x) ((x) << 0)
216 #define TMIN_MASK 0x000000FF
217 #define TMIN_SHIFT 0
222 #define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
225 #define CG_TACH_CTRL 0x1dc
226 # define EDGE_PER_REV(x) ((x) << 0)
227 # define EDGE_PER_REV_MASK (0x7 << 0)
228 # define EDGE_PER_REV_SHIFT 0
230 # define TARGET_PERIOD_MASK 0xfffffff8
232 #define CG_TACH_STATUS 0x1dd
233 # define TACH_PERIOD(x) ((x) << 0)
234 # define TACH_PERIOD_MASK 0xffffffff
235 # define TACH_PERIOD_SHIFT 0
237 #define GENERAL_PWRMGT 0x1e0
238 # define GLOBAL_PWRMGT_EN (1 << 0)
247 #define CG_TPC 0x1e1
248 #define SCLK_PWRMGT_CNTL 0x1e2
249 # define SCLK_PWRMGT_OFF (1 << 0)
263 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x1e6
264 # define CURRENT_STATE_INDEX_MASK (0xf << 4)
267 #define CG_FTV 0x1ef
269 #define CG_FFCT_0 0x1f0
270 # define UTC_0(x) ((x) << 0)
271 # define UTC_0_MASK (0x3ff << 0)
273 # define DTC_0_MASK (0x3ff << 10)
275 #define CG_BSP 0x1ff
276 # define BSP(x) ((x) << 0)
277 # define BSP_MASK (0xffff << 0)
279 # define BSU_MASK (0xf << 16)
280 #define CG_AT 0x200
281 # define CG_R(x) ((x) << 0)
282 # define CG_R_MASK (0xffff << 0)
284 # define CG_L_MASK (0xffff << 16)
286 #define CG_GIT 0x201
287 # define CG_GICST(x) ((x) << 0)
288 # define CG_GICST_MASK (0xffff << 0)
290 # define CG_GIPOT_MASK (0xffff << 16)
292 #define CG_SSP 0x203
293 # define SST(x) ((x) << 0)
294 # define SST_MASK (0xffff << 0)
296 # define SSTU_MASK (0xf << 16)
298 #define CG_DISPLAY_GAP_CNTL 0x20a
299 # define DISP1_GAP(x) ((x) << 0)
300 # define DISP1_GAP_MASK (3 << 0)
304 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
312 #define CG_ULV_CONTROL 0x21e
313 #define CG_ULV_PARAMETER 0x21f
315 #define SMC_SCRATCH0 0x221
317 #define CG_CAC_CTRL 0x22e
318 # define CAC_WINDOW(x) ((x) << 0)
319 # define CAC_WINDOW_MASK 0x00ffffff
321 #define DMIF_ADDR_CONFIG 0x2F5
323 #define DMIF_ADDR_CALC 0x300
325 #define PIPE0_DMIF_BUFFER_CONTROL 0x0328
326 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
329 #define SRBM_STATUS 0x394
339 #define SRBM_SOFT_RESET 0x398
355 #define CC_SYS_RB_BACKEND_DISABLE 0x3A0
356 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3A1
358 #define SRBM_READ_ERROR 0x3A6
359 #define SRBM_INT_CNTL 0x3A8
360 #define SRBM_INT_ACK 0x3AA
362 #define SRBM_STATUS2 0x3B1
366 #define VM_L2_CNTL 0x500
367 #define ENABLE_L2_CACHE (1 << 0)
375 #define VM_L2_CNTL2 0x501
376 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
379 #define INVALIDATE_PTE_AND_PDE_CACHES 0
382 #define VM_L2_CNTL3 0x502
383 #define BANK_SELECT(x) ((x) << 0)
387 #define VM_L2_STATUS 0x503
388 #define L2_BUSY (1 << 0)
389 #define VM_CONTEXT0_CNTL 0x504
390 #define ENABLE_CONTEXT (1 << 0)
404 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
405 #define VM_CONTEXT1_CNTL 0x505
406 #define VM_CONTEXT0_CNTL2 0x50C
407 #define VM_CONTEXT1_CNTL2 0x50D
408 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50E
409 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50F
410 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
411 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
412 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
413 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
414 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
415 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
417 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
418 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
419 #define PROTECTIONS_MASK (0xf << 0)
420 #define PROTECTIONS_SHIFT 0
421 /* bit 0: range
427 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
431 #define FAULT_VMID_MASK (0xf << 25)
434 #define VM_INVALIDATE_REQUEST 0x51E
435 #define VM_INVALIDATE_RESPONSE 0x51F
437 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
438 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
440 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F
441 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
442 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
443 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
444 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
445 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
446 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
447 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
448 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
449 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
451 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55F
452 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
454 #define VM_L2_CG 0x570
458 #define MC_SHARED_CHMAP 0x801
460 #define NOOFCHAN_MASK 0x0000f000
461 #define MC_SHARED_CHREMAP 0x802
463 #define MC_VM_FB_LOCATION 0x809
464 #define MC_VM_AGP_TOP 0x80A
465 #define MC_VM_AGP_BOT 0x80B
466 #define MC_VM_AGP_BASE 0x80C
467 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D
468 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E
469 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F
471 #define MC_VM_MX_L1_TLB_CNTL 0x819
472 #define ENABLE_L1_TLB (1 << 0)
474 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
478 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
481 #define MC_SHARED_BLACKOUT_CNTL 0x82B
483 #define MC_HUB_MISC_HUB_CG 0x82E
484 #define MC_HUB_MISC_VM_CG 0x82F
486 #define MC_HUB_MISC_SIP_CG 0x830
488 #define MC_XPB_CLK_GAT 0x91E
490 #define MC_CITF_MISC_RD_CG 0x992
491 #define MC_CITF_MISC_WR_CG 0x993
492 #define MC_CITF_MISC_VM_CG 0x994
494 #define MC_ARB_RAMCFG 0x9D8
495 #define NOOFBANK_SHIFT 0
496 #define NOOFBANK_MASK 0x00000003
498 #define NOOFRANK_MASK 0x00000004
500 #define NOOFROWS_MASK 0x00000038
502 #define NOOFCOLS_MASK 0x000000C0
504 #define CHANSIZE_MASK 0x00000100
507 #define NOOFGROUPS_MASK 0x00001000
509 #define MC_ARB_DRAM_TIMING 0x9DD
510 #define MC_ARB_DRAM_TIMING2 0x9DE
512 #define MC_ARB_BURST_TIME 0xA02
513 #define STATE0(x) ((x) << 0)
514 #define STATE0_MASK (0x1f << 0)
515 #define STATE0_SHIFT 0
517 #define STATE1_MASK (0x1f << 5)
520 #define STATE2_MASK (0x1f << 10)
523 #define STATE3_MASK (0x1f << 15)
526 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A
530 #define MC_SEQ_SUP_CNTL 0xA32
531 #define RUN_MASK (1 << 0)
532 #define MC_SEQ_SUP_PGM 0xA33
533 #define MC_PMG_AUTO_CMD 0xA34
535 #define MC_IO_PAD_CNTL_D0 0xA74
538 #define MC_SEQ_RAS_TIMING 0xA28
539 #define MC_SEQ_CAS_TIMING 0xA29
540 #define MC_SEQ_MISC_TIMING 0xA2A
541 #define MC_SEQ_MISC_TIMING2 0xA2B
542 #define MC_SEQ_PMG_TIMING 0xA2C
543 #define MC_SEQ_RD_CTL_D0 0xA2D
544 #define MC_SEQ_RD_CTL_D1 0xA2E
545 #define MC_SEQ_WR_CTL_D0 0xA2F
546 #define MC_SEQ_WR_CTL_D1 0xA30
548 #define MC_SEQ_MISC0 0xA80
550 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
553 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
556 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
558 #define MC_SEQ_MISC1 0xA81
559 #define MC_SEQ_RESERVE_M 0xA82
560 #define MC_PMG_CMD_EMRS 0xA83
562 #define MC_SEQ_IO_DEBUG_INDEX 0xA91
563 #define MC_SEQ_IO_DEBUG_DATA 0xA92
565 #define MC_SEQ_MISC5 0xA95
566 #define MC_SEQ_MISC6 0xA96
568 #define MC_SEQ_MISC7 0xA99
570 #define MC_SEQ_RAS_TIMING_LP 0xA9B
571 #define MC_SEQ_CAS_TIMING_LP 0xA9C
572 #define MC_SEQ_MISC_TIMING_LP 0xA9D
573 #define MC_SEQ_MISC_TIMING2_LP 0xA9E
574 #define MC_SEQ_WR_CTL_D0_LP 0xA9F
575 #define MC_SEQ_WR_CTL_D1_LP 0xAA0
576 #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1
577 #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2
579 #define MC_PMG_CMD_MRS 0xAAB
581 #define MC_SEQ_RD_CTL_D0_LP 0xAC7
582 #define MC_SEQ_RD_CTL_D1_LP 0xAC8
584 #define MC_PMG_CMD_MRS1 0xAD1
585 #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2
586 #define MC_SEQ_PMG_TIMING_LP 0xAD3
588 #define MC_SEQ_WR_CTL_2 0xAD5
589 #define MC_SEQ_WR_CTL_2_LP 0xAD6
590 #define MC_PMG_CMD_MRS2 0xAD7
591 #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8
593 #define MCLK_PWRMGT_CNTL 0xAE8
594 # define DLL_SPEED(x) ((x) << 0)
595 # define DLL_SPEED_MASK (0x1f << 0)
603 #define DLL_CNTL 0xAE9
607 #define MPLL_CNTL_MODE 0xAEC
609 #define MPLL_FUNC_CNTL 0xAED
611 #define BWCTRL_MASK (0xff << 20)
612 #define MPLL_FUNC_CNTL_1 0xAEE
613 #define VCO_MODE(x) ((x) << 0)
614 #define VCO_MODE_MASK (3 << 0)
616 #define CLKFRAC_MASK (0xfff << 4)
618 #define CLKF_MASK (0xfff << 16)
619 #define MPLL_FUNC_CNTL_2 0xAEF
620 #define MPLL_AD_FUNC_CNTL 0xAF0
621 #define YCLK_POST_DIV(x) ((x) << 0)
622 #define YCLK_POST_DIV_MASK (7 << 0)
623 #define MPLL_DQ_FUNC_CNTL 0xAF1
627 #define MPLL_SS1 0xAF3
628 #define CLKV(x) ((x) << 0)
629 #define CLKV_MASK (0x3ffffff << 0)
630 #define MPLL_SS2 0xAF4
631 #define CLKS(x) ((x) << 0)
632 #define CLKS_MASK (0xfff << 0)
634 #define HDP_HOST_PATH_CNTL 0xB00
636 #define HDP_NONSURFACE_BASE 0xB01
637 #define HDP_NONSURFACE_INFO 0xB02
638 #define HDP_NONSURFACE_SIZE 0xB03
640 #define HDP_DEBUG0 0xBCC
642 #define HDP_ADDR_CONFIG 0xBD2
643 #define HDP_MISC_CNTL 0xBD3
644 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
645 #define HDP_MEM_POWER_LS 0xBD4
646 #define HDP_LS_ENABLE (1 << 0)
648 #define ATC_MISC_CG 0xCD4
650 #define IH_RB_CNTL 0xF80
651 # define IH_RB_ENABLE (1 << 0)
658 #define IH_RB_BASE 0xF81
659 #define IH_RB_RPTR 0xF82
660 #define IH_RB_WPTR 0xF83
661 # define RB_OVERFLOW (1 << 0)
662 # define WPTR_OFFSET_MASK 0x3fffc
663 #define IH_RB_WPTR_ADDR_HI 0xF84
664 #define IH_RB_WPTR_ADDR_LO 0xF85
665 #define IH_CNTL 0xF86
666 # define ENABLE_INTR (1 << 0)
668 # define IH_MC_SWAP_NONE 0
677 #define CONFIG_MEMSIZE 0x150A
679 #define INTERRUPT_CNTL 0x151A
680 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
684 #define INTERRUPT_CNTL2 0x151B
686 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
688 #define BIF_FB_EN 0x1524
689 #define FB_READ_EN (1 << 0)
692 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528
695 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
696 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
697 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
698 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */
699 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */
700 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */
701 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */
702 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */
703 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (defaul…
704 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */
705 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
706 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
707 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */
708 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */
709 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
711 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
712 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
713 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
724 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
725 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
726 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
728 * 0 = invalid
732 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
733 # define HBR_CAPABLE (1 << 0) /* enabled by default */
735 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
736 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
737 # define PRODUCT_ID(x) (((x) & 0xffff) << 16)
738 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
739 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
740 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
741 # define PORT_ID0(x) (((x) & 0xffffffff) << 0)
742 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
743 # define PORT_ID1(x) (((x) & 0xffffffff) << 0)
744 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
745 # define DESCRIPTION0(x) (((x) & 0xff) << 0)
746 # define DESCRIPTION1(x) (((x) & 0xff) << 8)
747 # define DESCRIPTION2(x) (((x) & 0xff) << 16)
748 # define DESCRIPTION3(x) (((x) & 0xff) << 24)
749 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
750 # define DESCRIPTION4(x) (((x) & 0xff) << 0)
751 # define DESCRIPTION5(x) (((x) & 0xff) << 8)
752 # define DESCRIPTION6(x) (((x) & 0xff) << 16)
753 # define DESCRIPTION7(x) (((x) & 0xff) << 24)
754 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
755 # define DESCRIPTION8(x) (((x) & 0xff) << 0)
756 # define DESCRIPTION9(x) (((x) & 0xff) << 8)
757 # define DESCRIPTION10(x) (((x) & 0xff) << 16)
758 # define DESCRIPTION11(x) (((x) & 0xff) << 24)
759 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
760 # define DESCRIPTION12(x) (((x) & 0xff) << 0)
761 # define DESCRIPTION13(x) (((x) & 0xff) << 8)
762 # define DESCRIPTION14(x) (((x) & 0xff) << 16)
763 # define DESCRIPTION15(x) (((x) & 0xff) << 24)
764 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
765 # define DESCRIPTION16(x) (((x) & 0xff) << 0)
766 # define DESCRIPTION17(x) (((x) & 0xff) << 8)
768 #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
771 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
775 #define DC_LB_MEMORY_SPLIT 0x1AC3
778 #define PRIORITY_A_CNT 0x1AC6
779 #define PRIORITY_MARK_MASK 0x7fff
782 #define PRIORITY_B_CNT 0x1AC7
784 #define DPG_PIPE_ARBITRATION_CONTROL3 0x1B32
786 #define DPG_PIPE_LATENCY_CONTROL 0x1B33
787 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
790 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
791 #define VLINE_STATUS 0x1AEE
792 # define VLINE_OCCURRED (1 << 0)
797 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
798 #define VBLANK_STATUS 0x1AEF
799 # define VBLANK_OCCURRED (1 << 0)
805 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
806 #define INT_MASK 0x1AD0
807 # define VBLANK_INT_MASK (1 << 0)
810 #define DISP_INTERRUPT_STATUS 0x183D
819 #define DISP_INTERRUPT_STATUS_CONTINUE 0x183E
825 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x183F
830 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x1840
835 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x1853
840 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x1854
846 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
847 #define GRPH_INT_STATUS 0x1A16
848 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
850 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
851 #define GRPH_INT_CONTROL 0x1A17
852 # define GRPH_PFLIP_INT_MASK (1 << 0)
855 #define DAC_AUTODETECT_INT_CONTROL 0x19F2
857 #define DC_HPD1_INT_STATUS 0x1807
858 #define DC_HPD2_INT_STATUS 0x180A
859 #define DC_HPD3_INT_STATUS 0x180D
860 #define DC_HPD4_INT_STATUS 0x1810
861 #define DC_HPD5_INT_STATUS 0x1813
862 #define DC_HPD6_INT_STATUS 0x1816
863 # define DC_HPDx_INT_STATUS (1 << 0)
867 #define DC_HPD1_INT_CONTROL 0x1808
868 #define DC_HPD2_INT_CONTROL 0x180B
869 #define DC_HPD3_INT_CONTROL 0x180E
870 #define DC_HPD4_INT_CONTROL 0x1811
871 #define DC_HPD5_INT_CONTROL 0x1814
872 #define DC_HPD6_INT_CONTROL 0x1817
873 # define DC_HPDx_INT_ACK (1 << 0)
879 #define DC_HPD1_CONTROL 0x1809
880 #define DC_HPD2_CONTROL 0x180C
881 #define DC_HPD3_CONTROL 0x180F
882 #define DC_HPD4_CONTROL 0x1812
883 #define DC_HPD5_CONTROL 0x1815
884 #define DC_HPD6_CONTROL 0x1818
885 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
889 #define DPG_PIPE_STUTTER_CONTROL 0x1B35
890 # define STUTTER_ENABLE (1 << 0)
892 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
893 #define CRTC_STATUS_FRAME_COUNT 0x1BA6
896 #define DCCG_AUDIO_DTO0_PHASE 0x05b0
897 #define DCCG_AUDIO_DTO0_MODULE 0x05b4
898 #define DCCG_AUDIO_DTO1_PHASE 0x05c0
899 #define DCCG_AUDIO_DTO1_MODULE 0x05c4
901 #define GRBM_CNTL 0x2000
902 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
904 #define GRBM_STATUS2 0x2002
905 #define RLC_RQ_PENDING (1 << 0)
909 #define GRBM_STATUS 0x2004
910 #define CMDFIFO_AVAIL_MASK 0x0000000F
935 #define GRBM_STATUS_SE0 0x2005
936 #define GRBM_STATUS_SE1 0x2006
949 #define GRBM_INT_CNTL 0x2018
950 # define RDERR_INT_ENABLE (1 << 0)
953 #define CP_STRMOUT_CNTL 0x213F
954 #define SCRATCH_REG0 0x2140
955 #define SCRATCH_REG1 0x2141
956 #define SCRATCH_REG2 0x2142
957 #define SCRATCH_REG3 0x2143
958 #define SCRATCH_REG4 0x2144
959 #define SCRATCH_REG5 0x2145
960 #define SCRATCH_REG6 0x2146
961 #define SCRATCH_REG7 0x2147
963 #define SCRATCH_UMSK 0x2150
964 #define SCRATCH_ADDR 0x2151
966 #define CP_SEM_WAIT_TIMER 0x216F
968 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x2172
970 #define CP_ME_CNTL 0x21B6
975 #define CP_COHER_CNTL2 0x217A
977 #define CP_RB2_RPTR 0x21BE
978 #define CP_RB1_RPTR 0x21BF
979 #define CP_RB0_RPTR 0x21C0
980 #define CP_RB_WPTR_DELAY 0x21C1
982 #define CP_QUEUE_THRESHOLDS 0x21D8
983 #define ROQ_IB1_START(x) ((x) << 0)
985 #define CP_MEQ_THRESHOLDS 0x21D9
986 #define MEQ1_START(x) ((x) << 0)
989 #define CP_PERFMON_CNTL 0x21FF
991 #define VGT_VTX_VECT_EJECT_REG 0x222C
993 #define VGT_ESGS_RING_SIZE 0x2232
994 #define VGT_GSVS_RING_SIZE 0x2233
996 #define VGT_GS_VERTEX_REUSE 0x2235
998 #define VGT_PRIMITIVE_TYPE 0x2256
999 #define VGT_INDEX_TYPE 0x2257
1001 #define VGT_NUM_INDICES 0x225C
1002 #define VGT_NUM_INSTANCES 0x225D
1004 #define VGT_TF_RING_SIZE 0x2262
1006 #define VGT_HS_OFFCHIP_PARAM 0x226C
1008 #define VGT_TF_MEMORY_BASE 0x226E
1010 #define PA_CL_ENHANCE 0x2285
1011 #define CLIP_VTX_REORDER_ENA (1 << 0)
1014 #define PA_SU_LINE_STIPPLE_VALUE 0x2298
1016 #define PA_SC_LINE_STIPPLE_STATE 0x22C4
1018 #define PA_SC_FORCE_EOV_MAX_CNTS 0x22C9
1019 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1022 #define PA_SC_FIFO_SIZE 0x22F3
1023 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1028 #define PA_SC_ENHANCE 0x22FC
1030 #define SQ_CONFIG 0x2300
1032 #define SQC_CACHES 0x2302
1034 #define SQ_POWER_THROTTLE 0x2396
1035 #define MIN_POWER(x) ((x) << 0)
1036 #define MIN_POWER_MASK (0x3fff << 0)
1037 #define MIN_POWER_SHIFT 0
1039 #define MAX_POWER_MASK (0x3fff << 16)
1040 #define MAX_POWER_SHIFT 0
1041 #define SQ_POWER_THROTTLE2 0x2397
1042 #define MAX_POWER_DELTA(x) ((x) << 0)
1043 #define MAX_POWER_DELTA_MASK (0x3fff << 0)
1044 #define MAX_POWER_DELTA_SHIFT 0
1046 #define STI_SIZE_MASK (0x3ff << 16)
1049 #define LTI_RATIO_MASK (0xf << 27)
1052 #define SX_DEBUG_1 0x2418
1054 #define SPI_STATIC_THREAD_MGMT_1 0x2438
1055 #define SPI_STATIC_THREAD_MGMT_2 0x2439
1056 #define SPI_STATIC_THREAD_MGMT_3 0x243A
1057 #define SPI_PS_MAX_WAVE_ID 0x243B
1059 #define SPI_CONFIG_CNTL 0x2440
1061 #define SPI_CONFIG_CNTL_1 0x244F
1062 #define VTX_DONE_DELAY(x) ((x) << 0)
1065 #define CGTS_TCC_DISABLE 0x2452
1066 #define CGTS_USER_TCC_DISABLE 0x2453
1067 #define TCC_DISABLE_MASK 0xFFFF0000
1069 #define CGTS_SM_CTRL_REG 0x2454
1073 #define SPI_LB_CU_MASK 0x24D5
1075 #define TA_CNTL_AUX 0x2542
1077 #define CC_RB_BACKEND_DISABLE 0x263D
1079 #define GB_ADDR_CONFIG 0x263E
1080 #define NUM_PIPES(x) ((x) << 0)
1081 #define NUM_PIPES_MASK 0x00000007
1082 #define NUM_PIPES_SHIFT 0
1084 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1087 #define NUM_SHADER_ENGINES_MASK 0x00003000
1090 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1093 #define NUM_GPUS_MASK 0x00700000
1096 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
1099 #define ROW_SIZE_MASK 0x30000000
1102 #define CB_PERFCOUNTER0_SELECT0 0x2688
1103 #define CB_PERFCOUNTER0_SELECT1 0x2689
1104 #define CB_PERFCOUNTER1_SELECT0 0x268A
1105 #define CB_PERFCOUNTER1_SELECT1 0x268B
1106 #define CB_PERFCOUNTER2_SELECT0 0x268C
1107 #define CB_PERFCOUNTER2_SELECT1 0x268D
1108 #define CB_PERFCOUNTER3_SELECT0 0x268E
1109 #define CB_PERFCOUNTER3_SELECT1 0x268F
1111 #define CB_CGTT_SCLK_CTRL 0x2698
1113 #define TCP_CHAN_STEER_LO 0x2B03
1114 #define TCP_CHAN_STEER_HI 0x2B94
1116 #define CP_RB0_BASE 0x3040
1117 #define CP_RB0_CNTL 0x3041
1118 #define RB_BUFSZ(x) ((x) << 0)
1124 #define CP_RB0_RPTR_ADDR 0x3043
1125 #define CP_RB0_RPTR_ADDR_HI 0x3044
1126 #define CP_RB0_WPTR 0x3045
1128 #define CP_PFP_UCODE_ADDR 0x3054
1129 #define CP_PFP_UCODE_DATA 0x3055
1130 #define CP_ME_RAM_RADDR 0x3056
1131 #define CP_ME_RAM_WADDR 0x3057
1132 #define CP_ME_RAM_DATA 0x3058
1134 #define CP_CE_UCODE_ADDR 0x305A
1135 #define CP_CE_UCODE_DATA 0x305B
1137 #define CP_RB1_BASE 0x3060
1138 #define CP_RB1_CNTL 0x3061
1139 #define CP_RB1_RPTR_ADDR 0x3062
1140 #define CP_RB1_RPTR_ADDR_HI 0x3063
1141 #define CP_RB1_WPTR 0x3064
1142 #define CP_RB2_BASE 0x3065
1143 #define CP_RB2_CNTL 0x3066
1144 #define CP_RB2_RPTR_ADDR 0x3067
1145 #define CP_RB2_RPTR_ADDR_HI 0x3068
1146 #define CP_RB2_WPTR 0x3069
1147 #define CP_INT_CNTL_RING0 0x306A
1148 #define CP_INT_CNTL_RING1 0x306B
1149 #define CP_INT_CNTL_RING2 0x306C
1157 #define CP_INT_STATUS_RING0 0x306D
1158 #define CP_INT_STATUS_RING1 0x306E
1159 #define CP_INT_STATUS_RING2 0x306F
1166 // #define PA_SC_RASTER_CONFIG 0xA0D4
1168 # define RB_XSEL2_MASK (0x3 << 4)
1173 # define PKR_XSEL_MASK (0x3 << 10)
1175 # define PKR_YSEL_MASK (0x3 << 12)
1177 # define SC_MAP_MASK (0x3 << 16)
1179 # define SC_XSEL_MASK (0x3 << 18)
1181 # define SC_YSEL_MASK (0x3 << 20)
1184 # define SE_XSEL_MASK (0x3 << 26)
1186 # define SE_YSEL_MASK (0x3 << 28)
1188 /* PIF PHY0 registers idx/data 0x8/0xc */
1189 #define PB0_PIF_CNTL 0x10
1191 # define LS2_EXIT_TIME_MASK (0x7 << 17)
1193 #define PB0_PIF_PAIRING 0x11
1195 #define PB0_PIF_PWRDOWN_0 0x12
1197 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1200 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1203 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1205 #define PB0_PIF_PWRDOWN_1 0x13
1207 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1210 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1213 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1216 #define PB0_PIF_PWRDOWN_2 0x17
1218 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
1221 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
1224 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
1226 #define PB0_PIF_PWRDOWN_3 0x18
1228 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
1231 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
1234 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
1236 /* PIF PHY1 registers idx/data 0x10/0x14 */
1237 #define PB1_PIF_CNTL 0x10
1238 #define PB1_PIF_PAIRING 0x11
1239 #define PB1_PIF_PWRDOWN_0 0x12
1240 #define PB1_PIF_PWRDOWN_1 0x13
1242 #define PB1_PIF_PWRDOWN_2 0x17
1243 #define PB1_PIF_PWRDOWN_3 0x18
1244 /* PCIE registers idx/data 0x30/0x34 */
1245 #define PCIE_CNTL2 0x1c /* PCIE */
1250 #define PCIE_LC_STATUS1 0x28 /* PCIE */
1251 # define LC_REVERSE_RCVR (1 << 0)
1253 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1255 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
1258 #define PCIE_P_CNTL 0x40 /* PCIE */
1261 /* PCIE PORT registers idx/data 0x38/0x3c */
1262 #define PCIE_LC_CNTL 0xa0
1264 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
1267 # define LC_L1_INACTIVITY_MASK (0xf << 12)
1271 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1272 # define LC_LINK_WIDTH_SHIFT 0
1273 # define LC_LINK_WIDTH_MASK 0x7
1274 # define LC_LINK_WIDTH_X0 0
1281 # define LC_LINK_WIDTH_RD_MASK 0x70
1290 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1292 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
1293 # define LC_XMIT_N_FTS(x) ((x) << 0)
1294 # define LC_XMIT_N_FTS_MASK (0xff << 0)
1295 # define LC_XMIT_N_FTS_SHIFT 0
1297 # define LC_N_FTS_MASK (0xff << 24)
1298 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1299 # define LC_GEN2_EN_STRAP (1 << 0)
1302 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
1309 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
1311 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1319 #define PCIE_LC_CNTL2 0xb1
1323 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1325 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1332 #define UVD_UDEC_ADDR_CONFIG 0x3bd3
1333 #define UVD_UDEC_DB_ADDR_CONFIG 0x3bd4
1334 #define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
1335 #define UVD_RBC_RB_RPTR 0x3da4
1336 #define UVD_RBC_RB_WPTR 0x3da5
1337 #define UVD_STATUS 0x3daf
1339 #define UVD_CGC_CTRL 0x3dc2
1340 # define DCM (1 << 0)
1342 # define CG_DT_MASK (0xf << 2)
1344 # define CLK_OD_MASK (0x1f << 6)
1347 #define UVD_CGC_MEM_CTRL 0xC0
1348 #define UVD_CGC_CTRL2 0xC1
1349 # define DYN_OR_EN (1 << 0)
1352 # define G_DIV_ID_MASK (0x7 << 2)
1357 #define PACKET_TYPE0 0
1359 ((reg) & 0xFFFF) | \
1360 ((n) & 0x3FFF) << 16)
1361 #define CP_PACKET2 0x80000000
1362 #define PACKET2_PAD_SHIFT 0
1363 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1368 (((op) & 0xFF) << 8) | \
1369 ((n) & 0x3FFF) << 16)
1374 #define PACKET3_NOP 0x10
1375 #define PACKET3_SET_BASE 0x11
1376 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1379 #define PACKET3_CLEAR_STATE 0x12
1380 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1381 #define PACKET3_DISPATCH_DIRECT 0x15
1382 #define PACKET3_DISPATCH_INDIRECT 0x16
1383 #define PACKET3_ALLOC_GDS 0x1B
1384 #define PACKET3_WRITE_GDS_RAM 0x1C
1385 #define PACKET3_ATOMIC_GDS 0x1D
1386 #define PACKET3_ATOMIC 0x1E
1387 #define PACKET3_OCCLUSION_QUERY 0x1F
1388 #define PACKET3_SET_PREDICATION 0x20
1389 #define PACKET3_REG_RMW 0x21
1390 #define PACKET3_COND_EXEC 0x22
1391 #define PACKET3_PRED_EXEC 0x23
1392 #define PACKET3_DRAW_INDIRECT 0x24
1393 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1394 #define PACKET3_INDEX_BASE 0x26
1395 #define PACKET3_DRAW_INDEX_2 0x27
1396 #define PACKET3_CONTEXT_CONTROL 0x28
1397 #define PACKET3_INDEX_TYPE 0x2A
1398 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1399 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1400 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1401 #define PACKET3_NUM_INSTANCES 0x2F
1402 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1403 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
1404 #define PACKET3_INDIRECT_BUFFER 0x3F
1405 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1406 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1407 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1408 #define PACKET3_WRITE_DATA 0x37
1410 /* 0 - register
1420 /* 0 - me
1424 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1425 #define PACKET3_MEM_SEMAPHORE 0x39
1426 #define PACKET3_MPEG_INDEX 0x3A
1427 #define PACKET3_COPY_DW 0x3B
1428 #define PACKET3_WAIT_REG_MEM 0x3C
1429 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1430 /* 0 - always
1439 /* 0 - reg
1443 /* 0 - me
1446 #define PACKET3_MEM_WRITE 0x3D
1447 #define PACKET3_COPY_DATA 0x40
1448 #define PACKET3_CP_DMA 0x41
1450 * 2. SRC_ADDR_LO or DATA [31:0]
1452 * SRC_ADDR_HI [7:0]
1453 * 4. DST_ADDR_LO [31:0]
1454 * 5. DST_ADDR_HI [7:0]
1455 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1458 /* 0 - DST_ADDR
1462 /* 0 - ME
1466 /* 0 - SRC_ADDR
1474 /* 0 - none
1480 /* 0 - none
1486 /* 0 - memory
1490 /* 0 - memory
1496 #define PACKET3_PFP_SYNC_ME 0x42
1497 #define PACKET3_SURFACE_SYNC 0x43
1498 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1517 #define PACKET3_ME_INITIALIZE 0x44
1519 #define PACKET3_COND_WRITE 0x45
1520 #define PACKET3_EVENT_WRITE 0x46
1521 #define EVENT_TYPE(x) ((x) << 0)
1523 /* 0 - any non-TS event
1534 #define PACKET3_EVENT_WRITE_EOP 0x47
1536 /* 0 - discard
1542 /* 0 - none
1543 * 1 - interrupt only (DATA_SEL = 0)
1546 #define PACKET3_EVENT_WRITE_EOS 0x48
1547 #define PACKET3_PREAMBLE_CNTL 0x4A
1550 #define PACKET3_ONE_REG_WRITE 0x57
1551 #define PACKET3_LOAD_CONFIG_REG 0x5F
1552 #define PACKET3_LOAD_CONTEXT_REG 0x60
1553 #define PACKET3_LOAD_SH_REG 0x61
1554 #define PACKET3_SET_CONFIG_REG 0x68
1555 #define PACKET3_SET_CONFIG_REG_START 0x00002000
1556 #define PACKET3_SET_CONFIG_REG_END 0x00002c00
1557 #define PACKET3_SET_CONTEXT_REG 0x69
1558 #define PACKET3_SET_CONTEXT_REG_START 0x000a000
1559 #define PACKET3_SET_CONTEXT_REG_END 0x000a400
1560 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1561 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1562 #define PACKET3_SET_SH_REG 0x76
1563 #define PACKET3_SET_SH_REG_START 0x00002c00
1564 #define PACKET3_SET_SH_REG_END 0x00003000
1565 #define PACKET3_SET_SH_REG_OFFSET 0x77
1566 #define PACKET3_ME_WRITE 0x7A
1567 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1568 #define PACKET3_SCRATCH_RAM_READ 0x7E
1569 #define PACKET3_CE_WRITE 0x7F
1570 #define PACKET3_LOAD_CONST_RAM 0x80
1571 #define PACKET3_WRITE_CONST_RAM 0x81
1572 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1573 #define PACKET3_DUMP_CONST_RAM 0x83
1574 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1575 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1576 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1577 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
1578 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1579 #define PACKET3_SET_CE_DE_COUNTERS 0x89
1580 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1581 #define PACKET3_SWITCH_BUFFER 0x8B
1583 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1584 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1585 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */
1587 #define DMA_RB_CNTL 0x3400
1588 # define DMA_RB_ENABLE (1 << 0)
1594 #define DMA_RB_BASE 0x3401
1595 #define DMA_RB_RPTR 0x3402
1596 #define DMA_RB_WPTR 0x3403
1598 #define DMA_RB_RPTR_ADDR_HI 0x3407
1599 #define DMA_RB_RPTR_ADDR_LO 0x3408
1601 #define DMA_IB_CNTL 0x3409
1602 # define DMA_IB_ENABLE (1 << 0)
1605 #define DMA_IB_RPTR 0x340a
1606 #define DMA_CNTL 0x340b
1607 # define TRAP_ENABLE (1 << 0)
1613 #define DMA_STATUS_REG 0x340d
1614 # define DMA_IDLE (1 << 0)
1615 #define DMA_TILING_CONFIG 0x342e
1617 #define DMA_POWER_CNTL 0x342f
1619 #define DMA_CLK_CTRL 0x3430
1621 #define DMA_PG 0x3435
1622 # define PG_CNTL_ENABLE (1 << 0)
1623 #define DMA_PGFSM_CONFIG 0x3436
1624 #define DMA_PGFSM_WRITE 0x3437
1626 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1627 (((b) & 0x1) << 26) | \
1628 (((t) & 0x1) << 23) | \
1629 (((s) & 0x1) << 22) | \
1630 (((n) & 0xFFFFF) << 0))
1632 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1633 (((vmid) & 0xF) << 20) | \
1634 (((n) & 0xFFFFF) << 0))
1639 (((n) & 0xFFFFF) << 0))
1642 #define DMA_PACKET_WRITE 0x2
1643 #define DMA_PACKET_COPY 0x3
1644 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1645 #define DMA_PACKET_SEMAPHORE 0x5
1646 #define DMA_PACKET_FENCE 0x6
1647 #define DMA_PACKET_TRAP 0x7
1648 #define DMA_PACKET_SRBM_WRITE 0x9
1649 #define DMA_PACKET_CONSTANT_FILL 0xd
1650 #define DMA_PACKET_POLL_REG_MEM 0xe
1651 #define DMA_PACKET_NOP 0xf
1653 #define VCE_STATUS 0x20004
1654 #define VCE_VCPU_CNTL 0x20014
1655 #define VCE_CLK_EN (1 << 0)
1656 #define VCE_VCPU_CACHE_OFFSET0 0x20024
1657 #define VCE_VCPU_CACHE_SIZE0 0x20028
1658 #define VCE_VCPU_CACHE_OFFSET1 0x2002c
1659 #define VCE_VCPU_CACHE_SIZE1 0x20030
1660 #define VCE_VCPU_CACHE_OFFSET2 0x20034
1661 #define VCE_VCPU_CACHE_SIZE2 0x20038
1662 #define VCE_SOFT_RESET 0x20120
1663 #define VCE_ECPU_SOFT_RESET (1 << 0)
1665 #define VCE_RB_BASE_LO2 0x2016c
1666 #define VCE_RB_BASE_HI2 0x20170
1667 #define VCE_RB_SIZE2 0x20174
1668 #define VCE_RB_RPTR2 0x20178
1669 #define VCE_RB_WPTR2 0x2017c
1670 #define VCE_RB_BASE_LO 0x20180
1671 #define VCE_RB_BASE_HI 0x20184
1672 #define VCE_RB_SIZE 0x20188
1673 #define VCE_RB_RPTR 0x2018c
1674 #define VCE_RB_WPTR 0x20190
1675 #define VCE_CLOCK_GATING_A 0x202f8
1676 #define VCE_CLOCK_GATING_B 0x202fc
1677 #define VCE_UENC_CLOCK_GATING 0x205bc
1678 #define VCE_UENC_REG_CLOCK_GATING 0x205c0
1679 #define VCE_FW_REG_STATUS 0x20e10
1680 # define VCE_FW_REG_STATUS_BUSY (1 << 0)
1683 #define VCE_LMI_FW_START_KEYSEL 0x20e18
1684 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
1685 #define VCE_LMI_CTRL2 0x20e74
1686 #define VCE_LMI_CTRL 0x20e98
1687 #define VCE_LMI_VM_CTRL 0x20ea0
1688 #define VCE_LMI_SWAP_CNTL 0x20eb4
1689 #define VCE_LMI_SWAP_CNTL1 0x20eb8
1690 #define VCE_LMI_CACHE_CTRL 0x20ef4
1692 #define VCE_CMD_NO_OP 0x00000000
1693 #define VCE_CMD_END 0x00000001
1694 #define VCE_CMD_IB 0x00000002
1695 #define VCE_CMD_FENCE 0x00000003
1696 #define VCE_CMD_TRAP 0x00000004
1697 #define VCE_CMD_IB_AUTO 0x00000005
1698 #define VCE_CMD_SEMAPHORE 0x00000006
1703 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4
1704 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4
1705 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4
1706 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4
1707 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4
1708 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4
1711 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
1712 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
1713 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
1714 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
1715 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
1716 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
1719 #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780)
1720 #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780)
1721 #define AUD2_REGISTER_OFFSET (0x178c - 0x1780)
1722 #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780)
1723 #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780)
1724 #define AUD5_REGISTER_OFFSET (0x179d - 0x1780)
1725 #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780)
1729 #define AMDGPU_MM_INDEX 0x0000
1730 #define AMDGPU_MM_DATA 0x0001
1733 #define BLACKOUT_MODE_MASK 0x00000007
1734 #define VGA_RENDER_CONTROL 0xC0
1735 #define R_000300_VGA_RENDER_CONTROL 0xC0
1736 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
1737 #define EVERGREEN_CRTC_STATUS 0x1BA3
1738 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
1739 #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4
1740 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
1741 #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d
1742 #define EVERGREEN_CRTC_CONTROL 0x1b9c
1743 #define EVERGREEN_CRTC_MASTER_EN (1 << 0)
1745 #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d
1747 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
1748 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8
1749 #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5
1750 #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd
1751 #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe
1753 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
1754 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
1755 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
1756 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
1757 #define EVERGREEN_GRPH_UPDATE 0x1a11
1758 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4
1759 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
1762 #define EVERGREEN_DATA_FORMAT 0x1ac0
1763 # define EVERGREEN_INTERLEAVE_EN (1 << 0)
1765 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
1770 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a45
1771 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1845
1773 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847
1774 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47
1776 #define R600_D1GRPH_SWAP_CONTROL 0x1843
1777 #define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
1778 #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
1779 #define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
1780 #define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
1782 #define AVIVO_D1VGA_CONTROL 0x00cc
1783 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)
1789 #define AVIVO_D2VGA_CONTROL 0x00ce
1791 #define R600_BUS_CNTL 0x1508
1794 #define R600_ROM_CNTL 0x580
1797 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
1799 #define FMT_BIT_DEPTH_CONTROL 0x1bf2
1800 #define FMT_TRUNCATE_EN (1 << 0)
1817 #define EVERGREEN_DC_LUT_CONTROL 0x1a80
1818 #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
1819 #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
1820 #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x1a83
1821 #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
1822 #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
1823 #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x1a86
1824 #define EVERGREEN_DC_LUT_30_COLOR 0x1a7c
1825 #define EVERGREEN_DC_LUT_RW_INDEX 0x1a79
1826 #define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x1a7e
1827 #define EVERGREEN_DC_LUT_RW_MODE 0x1a78
1829 #define EVERGREEN_GRPH_ENABLE 0x1a00
1830 #define EVERGREEN_GRPH_CONTROL 0x1a01
1831 #define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)
1832 #define EVERGREEN_GRPH_DEPTH_8BPP 0
1835 #define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
1836 #define EVERGREEN_ADDR_SURF_2_BANK 0
1840 #define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4)
1841 #define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
1842 #define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0
1846 #define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
1848 #define EVERGREEN_GRPH_FORMAT_INDEXED 0
1849 #define EVERGREEN_GRPH_FORMAT_ARGB1555 0
1857 #define EVERGREEN_GRPH_FORMAT_ARGB8888 0
1865 #define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
1866 #define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0
1870 #define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
1871 #define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0
1878 #define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
1879 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0
1883 #define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
1884 #define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0
1888 #define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0
1893 #define EVERGREEN_GRPH_SWAP_CONTROL 0x1a03
1894 #define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
1895 # define EVERGREEN_GRPH_ENDIAN_NONE 0
1899 #define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
1900 # define EVERGREEN_GRPH_RED_SEL_R 0
1904 #define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
1905 # define EVERGREEN_GRPH_GREEN_SEL_G 0
1909 #define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
1910 # define EVERGREEN_GRPH_BLUE_SEL_B 0
1914 #define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
1915 # define EVERGREEN_GRPH_ALPHA_SEL_A 0
1920 #define EVERGREEN_D3VGA_CONTROL 0xf8
1921 #define EVERGREEN_D4VGA_CONTROL 0xf9
1922 #define EVERGREEN_D5VGA_CONTROL 0xfa
1923 #define EVERGREEN_D6VGA_CONTROL 0xfb
1925 #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00
1927 #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02
1930 #define EVERGREEN_GRPH_PITCH 0x1a06
1931 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
1932 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
1933 #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x1a09
1934 #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x1a0a
1935 #define EVERGREEN_GRPH_X_START 0x1a0b
1936 #define EVERGREEN_GRPH_Y_START 0x1a0c
1937 #define EVERGREEN_GRPH_X_END 0x1a0d
1938 #define EVERGREEN_GRPH_Y_END 0x1a0e
1939 #define EVERGREEN_GRPH_UPDATE 0x1a11
1942 #define EVERGREEN_GRPH_FLIP_CONTROL 0x1a12
1943 #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
1945 #define EVERGREEN_VIEWPORT_START 0x1b5c
1946 #define EVERGREEN_VIEWPORT_SIZE 0x1b5d
1947 #define EVERGREEN_DESKTOP_HEIGHT 0x1ac1
1949 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
1950 #define EVERGREEN_CUR_CONTROL 0x1a66
1951 # define EVERGREEN_CURSOR_EN (1 << 0)
1952 # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)
1953 # define EVERGREEN_CURSOR_MONO 0
1959 # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
1960 # define EVERGREEN_CURSOR_URGENT_ALWAYS 0
1965 #define EVERGREEN_CUR_SURFACE_ADDRESS 0x1a67
1966 # define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000
1967 #define EVERGREEN_CUR_SIZE 0x1a68
1968 #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x1a69
1969 #define EVERGREEN_CUR_POSITION 0x1a6a
1970 #define EVERGREEN_CUR_HOT_SPOT 0x1a6b
1971 #define EVERGREEN_CUR_COLOR1 0x1a6c
1972 #define EVERGREEN_CUR_COLOR2 0x1a6d
1973 #define EVERGREEN_CUR_UPDATE 0x1a6e
1974 # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
1980 #define NI_INPUT_CSC_CONTROL 0x1a35
1981 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)
1982 # define NI_INPUT_CSC_BYPASS 0
1985 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)
1987 #define NI_OUTPUT_CSC_CONTROL 0x1a3c
1988 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0)
1989 # define NI_OUTPUT_CSC_BYPASS 0
1995 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4)
1997 #define NI_DEGAMMA_CONTROL 0x1a58
1998 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)
1999 # define NI_DEGAMMA_BYPASS 0
2002 # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)
2003 # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
2004 # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12)
2006 #define NI_GAMUT_REMAP_CONTROL 0x1a59
2007 # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0)
2008 # define NI_GAMUT_REMAP_BYPASS 0
2012 # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4)
2014 #define NI_REGAMMA_CONTROL 0x1aa0
2015 # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0)
2016 # define NI_REGAMMA_BYPASS 0
2021 # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4)
2024 #define NI_PRESCALE_GRPH_CONTROL 0x1a2d
2027 #define NI_PRESCALE_OVL_CONTROL 0x1a31
2030 #define NI_INPUT_GAMMA_CONTROL 0x1a10
2031 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)
2032 # define NI_INPUT_GAMMA_USE_LUT 0
2036 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
2038 #define BLACKOUT_MODE_MASK 0x00000007
2039 #define VGA_RENDER_CONTROL 0xC0
2040 #define R_000300_VGA_RENDER_CONTROL 0xC0
2041 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
2042 #define EVERGREEN_CRTC_STATUS 0x1BA3
2043 #define EVERGREEN_CRTC_V_BLANK (1 << 0)
2044 #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4
2045 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
2046 #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d
2047 #define EVERGREEN_CRTC_CONTROL 0x1b9c
2048 # define EVERGREEN_CRTC_MASTER_EN (1 << 0)
2050 #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d
2052 # define EVERGREEN_CRTC_V_BLANK (1 << 0)
2053 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8
2054 #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5
2055 #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd
2056 #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe
2058 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
2059 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
2060 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
2061 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
2062 #define EVERGREEN_GRPH_UPDATE 0x1a11
2063 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4
2064 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
2067 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
2068 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
2069 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
2070 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
2071 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
2072 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
2073 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
2074 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
2075 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
2076 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
2077 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
2078 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
2080 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000
2081 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19
2082 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff
2083 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0
2084 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000
2085 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc
2086 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000
2087 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18
2089 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7
2090 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0
2092 #define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1
2093 #define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0
2094 #define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2
2095 #define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1
2097 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000
2098 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11
2099 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800
2100 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb
2102 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
2103 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
2104 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
2105 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
2106 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
2107 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
2108 #define MC_SEQ_MISC0__MT__HBM 0x60000000
2109 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
2111 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2112 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
2113 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
2114 #define PACKET3_SEM_SEL_WAIT (0x7 << 29)
2116 #define CONFIG_CNTL 0x1509
2117 #define CC_DRM_ID_STRAPS 0X1559
2118 #define AMDGPU_PCIE_INDEX 0xc
2119 #define AMDGPU_PCIE_DATA 0xd
2121 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0x3411
2122 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0x3412
2123 #define DMA_MODE 0x342f
2124 #define DMA_RB_RPTR_ADDR_HI 0x3407
2125 #define DMA_RB_RPTR_ADDR_LO 0x3408
2126 #define DMA_BUSY_MASK 0x20
2127 #define DMA1_BUSY_MASK 0X40
2132 #define PCIE_PORT_INDEX 0xe
2133 #define PCIE_PORT_DATA 0xf
2134 #define EVERGREEN_PIF_PHY0_INDEX 0x8
2135 #define EVERGREEN_PIF_PHY0_DATA 0xc
2136 #define EVERGREEN_PIF_PHY1_INDEX 0x10
2137 #define EVERGREEN_PIF_PHY1_DATA 0x14
2139 #define MC_VM_FB_OFFSET 0x81a
2142 #define CG_VCEPLL_FUNC_CNTL 0xc0030600
2143 #define VCEPLL_RESET_MASK 0x00000001
2144 #define VCEPLL_SLEEP_MASK 0x00000002
2145 #define VCEPLL_BYPASS_EN_MASK 0x00000004
2146 #define VCEPLL_CTLREQ_MASK 0x00000008
2147 #define VCEPLL_VCO_MODE_MASK 0x00000600
2148 #define VCEPLL_REF_DIV_MASK 0x003F0000
2149 #define VCEPLL_CTLACK_MASK 0x40000000
2150 #define VCEPLL_CTLACK2_MASK 0x80000000
2152 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601
2153 #define VCEPLL_PDIV_A(x) ((x) << 0)
2154 #define VCEPLL_PDIV_A_MASK 0x0000007F
2156 #define VCEPLL_PDIV_B_MASK 0x00007F00
2158 #define EVCLK_SRC_SEL_MASK 0x01F00000
2160 #define ECCLK_SRC_SEL_MASK 0x3E000000
2162 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602
2163 #define VCEPLL_FB_DIV(x) ((x) << 0)
2164 #define VCEPLL_FB_DIV_MASK 0x01FFFFFF
2166 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603
2168 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604
2169 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606
2170 #define VCEPLL_SSEN_MASK 0x00000001