Lines Matching +full:poll +full:- +full:retry +full:- +full:count
43 return *ring->rptr_cpu_addr; in si_dma_ring_get_rptr()
48 struct amdgpu_device *adev = ring->adev; in si_dma_ring_get_wptr()
49 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_get_wptr()
56 struct amdgpu_device *adev = ring->adev; in si_dma_ring_set_wptr()
57 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; in si_dma_ring_set_wptr()
59 WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); in si_dma_ring_set_wptr()
71 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
75 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
80 * si_dma_ring_emit_fence - emit a fence on the DMA ring
118 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_stop()
133 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_start()
134 ring = &adev->sdma.instance[i].ring; in si_dma_start()
140 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
151 rptr_addr = ring->rptr_gpu_addr; in si_dma_start()
158 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
171 ring->wptr = 0; in si_dma_start()
172 WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2); in si_dma_start()
184 * si_dma_ring_test_ring - simple async dma engine test
194 struct amdgpu_device *adev = ring->adev; in si_dma_ring_test_ring()
205 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ring()
207 adev->wb.wb[index] = cpu_to_le32(tmp); in si_dma_ring_test_ring()
219 for (i = 0; i < adev->usec_timeout; i++) { in si_dma_ring_test_ring()
220 tmp = le32_to_cpu(adev->wb.wb[index]); in si_dma_ring_test_ring()
226 if (i >= adev->usec_timeout) in si_dma_ring_test_ring()
227 r = -ETIMEDOUT; in si_dma_ring_test_ring()
235 * si_dma_ring_test_ib - test an IB on the DMA engine
245 struct amdgpu_device *adev = ring->adev; in si_dma_ring_test_ib()
257 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ib()
259 adev->wb.wb[index] = cpu_to_le32(tmp); in si_dma_ring_test_ib()
277 r = -ETIMEDOUT; in si_dma_ring_test_ib()
282 tmp = le32_to_cpu(adev->wb.wb[index]); in si_dma_ring_test_ib()
286 r = -EINVAL; in si_dma_ring_test_ib()
297 * si_dma_vm_copy_pte - update PTEs by copying them from the GART
302 * @count: number of page entries to update
308 unsigned count) in si_dma_vm_copy_pte() argument
310 unsigned bytes = count * 8; in si_dma_vm_copy_pte()
312 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_vm_copy_pte()
314 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
315 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
316 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
317 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
321 * si_dma_vm_write_pte - update PTEs by writing them manually
326 * @count: number of page entries to update
332 uint64_t value, unsigned count, in si_dma_vm_write_pte() argument
335 unsigned ndw = count * 2; in si_dma_vm_write_pte()
337 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); in si_dma_vm_write_pte()
338 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
339 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte()
340 for (; ndw > 0; ndw -= 2) { in si_dma_vm_write_pte()
341 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
342 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pte()
348 * si_dma_vm_set_pte_pde - update the page tables using sDMA
353 * @count: number of page entries to update
361 uint64_t addr, unsigned count, in si_dma_vm_set_pte_pde() argument
367 while (count) { in si_dma_vm_set_pte_pde()
368 ndw = count * 2; in si_dma_vm_set_pte_pde()
378 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); in si_dma_vm_set_pte_pde()
379 ib->ptr[ib->length_dw++] = pe; /* dst addr */ in si_dma_vm_set_pte_pde()
380 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pte_pde()
381 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ in si_dma_vm_set_pte_pde()
382 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in si_dma_vm_set_pte_pde()
383 ib->ptr[ib->length_dw++] = value; /* value */ in si_dma_vm_set_pte_pde()
384 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pte_pde()
385 ib->ptr[ib->length_dw++] = incr; /* increment size */ in si_dma_vm_set_pte_pde()
386 ib->ptr[ib->length_dw++] = 0; in si_dma_vm_set_pte_pde()
389 count -= ndw / 2; in si_dma_vm_set_pte_pde()
394 * si_dma_ring_pad_ib - pad the IB to the required number of dw
402 while (ib->length_dw & 0x7) in si_dma_ring_pad_ib()
403 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); in si_dma_ring_pad_ib()
407 * si_dma_ring_emit_pipeline_sync - sync the pipeline
415 uint32_t seq = ring->fence_drv.sync_seq; in si_dma_ring_emit_pipeline_sync()
416 uint64_t addr = ring->fence_drv.gpu_addr; in si_dma_ring_emit_pipeline_sync()
420 (1 << 27)); /* Poll memory */ in si_dma_ring_emit_pipeline_sync()
422 amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */ in si_dma_ring_emit_pipeline_sync()
425 amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */ in si_dma_ring_emit_pipeline_sync()
429 * si_dma_ring_emit_vm_flush - cik vm flush using sDMA
446 amdgpu_ring_write(ring, 0xff << 16); /* retry */ in si_dma_ring_emit_vm_flush()
449 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ in si_dma_ring_emit_vm_flush()
462 struct amdgpu_device *adev = ip_block->adev; in si_dma_early_init()
464 adev->sdma.num_instances = 2; in si_dma_early_init()
478 struct amdgpu_device *adev = ip_block->adev; in si_dma_sw_init()
482 &adev->sdma.trap_irq); in si_dma_sw_init()
488 &adev->sdma.trap_irq); in si_dma_sw_init()
492 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_sw_init()
493 ring = &adev->sdma.instance[i].ring; in si_dma_sw_init()
494 ring->ring_obj = NULL; in si_dma_sw_init()
495 ring->use_doorbell = false; in si_dma_sw_init()
496 sprintf(ring->name, "sdma%d", i); in si_dma_sw_init()
498 &adev->sdma.trap_irq, in si_dma_sw_init()
511 struct amdgpu_device *adev = ip_block->adev; in si_dma_sw_fini()
514 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_sw_fini()
515 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in si_dma_sw_fini()
522 struct amdgpu_device *adev = ip_block->adev; in si_dma_hw_init()
529 si_dma_stop(ip_block->adev); in si_dma_hw_fini()
546 struct amdgpu_device *adev = ip_block->adev; in si_dma_is_idle()
559 struct amdgpu_device *adev = ip_block->adev; in si_dma_wait_for_idle()
561 for (i = 0; i < adev->usec_timeout; i++) { in si_dma_wait_for_idle()
566 return -ETIMEDOUT; in si_dma_wait_for_idle()
571 DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n"); in si_dma_soft_reset()
625 if (entry->src_id == 224) in si_dma_process_trap_irq()
626 amdgpu_fence_process(&adev->sdma.instance[0].ring); in si_dma_process_trap_irq()
628 amdgpu_fence_process(&adev->sdma.instance[1].ring); in si_dma_process_trap_irq()
638 struct amdgpu_device *adev = ip_block->adev; in si_dma_set_clockgating_state()
642 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { in si_dma_set_clockgating_state()
643 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
655 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
680 struct amdgpu_device *adev = ip_block->adev; in si_dma_set_powergating_state()
736 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_set_ring_funcs()
737 adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs; in si_dma_set_ring_funcs()
747 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; in si_dma_set_irq_funcs()
748 adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs; in si_dma_set_irq_funcs()
752 * si_dma_emit_copy_buffer - copy buffer using the sDMA engine
770 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_emit_copy_buffer()
772 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_copy_buffer()
773 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in si_dma_emit_copy_buffer()
774 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; in si_dma_emit_copy_buffer()
775 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; in si_dma_emit_copy_buffer()
779 * si_dma_emit_fill_buffer - fill buffer using the sDMA engine
793 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, in si_dma_emit_fill_buffer()
795 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_fill_buffer()
796 ib->ptr[ib->length_dw++] = src_data; in si_dma_emit_fill_buffer()
797 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; in si_dma_emit_fill_buffer()
813 adev->mman.buffer_funcs = &si_dma_buffer_funcs; in si_dma_set_buffer_funcs()
814 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in si_dma_set_buffer_funcs()
829 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
830 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_vm_pte_funcs()
831 adev->vm_manager.vm_pte_scheds[i] = in si_dma_set_vm_pte_funcs()
832 &adev->sdma.instance[i].ring.sched; in si_dma_set_vm_pte_funcs()
834 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()