Lines Matching +full:ip +full:- +full:76
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
94 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
96 GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
112 /* PSP boot config sub-commands */
194 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/
208 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
209 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
210 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
211 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
212 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
213 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
214 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
215 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
218 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
219 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
230 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
231 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
278 GFX_FW_TYPE_RS64_MES = 76, /* RS64 MES ucode SOC21 */
288 GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */
308 /* Command to load HW IP FW. */
318 /* Command to save/restore HW IP FW. */
346 …enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process com…
395 /* Command-specific response for Fw Attestation Db */
402 /* Command-specific response for boot config. */
407 /* Union of command-specific responses for GPCOM ring. */
428 union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */
451 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
458 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];