Lines Matching +full:32 +full:- +full:bits
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
73 … volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
112 /* PSP boot config sub-commands */
129 …uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary…
130 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
132 …uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (m…
133 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
155 …uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must b…
156 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
189 …uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must b…
190 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
194 uint32_t sriov_enabled:1; /* whether the device runs under SR-IOV*/
200 …uint32_t system_phy_addr_lo; /* bits [31:0] of system physical address of TMR buffer…
201 …uint32_t system_phy_addr_hi; /* bits [63:32] of system physical address of TMR buffe…
208 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
209 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
210 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
211 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
212 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
213 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
214 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
215 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
218 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
219 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
230 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
231 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
239 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
288 GFX_FW_TYPE_USB_DP_COMBO_PHY = 86, /* USB-Display port Combo SOC21 */
311 …uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (m…
312 …uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
322 …uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as …
323 …uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as…
337 …uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must…
338 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
346 …enum psp_gfx_boot_config_cmd sub_cmd; /* sub-command indicating how to process com…
348 …uint32_t boot_config_valid; /* dynamic boot configuration valid bits bit…
395 /* Command-specific response for Fw Attestation Db */
402 /* Command-specific response for boot config. */
407 /* Union of command-specific responses for GPCOM ring. */
422 …uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw co…
423 …uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw c…
428 union psp_gfx_uresp uresp; /* +64 response union containing command-specific responses */
444 …uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (…
445 …uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer …
451 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
458 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
469 …uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must …
470 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
472 …uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame …
473 …uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame…
475 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
476 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
477 …uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame…