Lines Matching +full:1 +full:x
31 #define PACKET_TYPE1 1
52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
57 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
67 #define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0) argument
68 #define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8) argument
69 #define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) argument
70 #define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x))) argument
71 #define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x))) argument
72 #define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x))) argument
73 #define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x))) argument
74 #define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x))) argument
75 #define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x))) argument
76 #define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0) argument
78 #define PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1
82 #define PACKET3_ATOMIC_MEM__CACHE_POLICY__STREAM 1
107 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
109 * 1 - memory (sync - via GRBM)
115 #define WR_ONE_ADDR (1 << 16)
116 #define WR_CONFIRM (1 << 20)
117 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
119 * 1 - Stream
121 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
123 * 1 - pfp
126 #define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) argument
127 #define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16) argument
128 #define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) argument
129 #define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) argument
130 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0) argument
131 #define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
132 #define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) argument
133 #define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x)) argument
134 #define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21) argument
135 #define PACKET3_WRITE_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 22) argument
136 #define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 24) argument
137 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x)) argument
138 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0xFF) << 0) argument
145 #define PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1
147 #define PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1
149 #define PACKET3_WRITE_DATA__MODE__PF_VF_ENABLED 1
151 #define PACKET3_WRITE_DATA__TEMPORAL__NT 1
155 #define PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1
161 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
167 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
169 * 1 - <
176 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
178 * 1 - mem
180 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) argument
182 * 1 - wr_wait_wr_reg
184 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
186 * 1 - pfp
188 #define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0) argument
189 #define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4) argument
190 #define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6) argument
191 #define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22) argument
192 #define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24) argument
193 #define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) argument
194 #define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) argument
195 #define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) argument
196 #define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) & 0X3FFFF) << 0) argument
197 #define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0X3FFFF) << 0) argument
198 #define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x)) argument
199 #define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0) argument
200 #define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x)) argument
201 #define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) argument
202 #define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
203 #define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31) argument
205 #define PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1
212 #define PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1
214 #define PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1
217 #define PACKET3_WAIT_REG_MEM__CACHE_POLICY__STREAM 1
221 #define PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1
225 #define INDIRECT_BUFFER_VALID (1 << 23)
226 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) argument
228 * 1 - Stream
231 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
232 #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) argument
233 #define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) argument
234 #define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x)) argument
235 #define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0) argument
236 #define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20) argument
237 #define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21) argument
238 #define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23) argument
239 #define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24) argument
240 #define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 28) argument
241 #define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28) argument
242 #define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31) argument
244 #define PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1
248 #define PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1
253 #define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0) argument
254 #define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8) argument
255 #define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 13) argument
256 #define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13) argument
257 #define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16) argument
258 #define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20) argument
259 #define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25) argument
260 #define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29) argument
261 #define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0) argument
262 #define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) argument
263 #define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) argument
264 #define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
265 #define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x)) argument
266 #define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x)) argument
267 #define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x)) argument
268 #define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0) argument
269 #define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2) argument
270 #define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) argument
271 #define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
272 #define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x)) argument
273 #define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21) argument
274 #define PACKET3_COPY_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 23) argument
275 #define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25) argument
276 #define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x)) argument
277 #define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0) argument
278 #define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x)) argument
279 #define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0) argument
281 #define PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1
298 #define PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1
302 #define PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1
306 #define PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1
308 #define PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1
310 #define PACKET3_COPY_DATA__MODE__PF_VF_ENABLED 1
312 #define PACKET3_COPY_DATA__DST_TEMPORAL__NT 1
316 #define PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1
320 #define PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1
327 #define EVENT_TYPE(x) ((x) << 0) argument
328 #define EVENT_INDEX(x) ((x) << 8) argument
330 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
335 #define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0) argument
336 #define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8) argument
337 #define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) & 0x3) << 29) argument
338 #define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 0) argument
339 #define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3) argument
340 #define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x)) argument
349 #define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE1 1
355 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) argument
356 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) argument
357 #define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12)
358 #define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13)
359 #define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14)
360 #define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15)
361 #define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16)
362 #define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17)
363 #define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19)
364 #define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20)
365 #define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21)
366 #define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22)
367 #define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) argument
369 * 1 - cache_policy__me_release_mem__stream
373 #define PACKET3_RELEASE_MEM_EXECUTE (1 << 28)
375 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) argument
377 * 1 - send low 32bit data
382 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) argument
384 * 1 - interrupt only (DATA_SEL = 0)
387 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) argument
389 * 1 - TC/L2
398 /* 1. header
407 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) argument
409 * 1 - PFP
411 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) argument
413 * 1 - Stream
415 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) argument
417 * 1 - GDS
420 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) argument
422 * 1 - Stream
424 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) argument
426 * 1 - GDS
430 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
432 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
434 * 1 - register
436 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
438 * 1 - register
440 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
441 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
442 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
448 /* 1. HEADER
458 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) argument
461 * 1:ALL
465 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) argument
468 * 1:reserved
472 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) argument
473 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) argument
474 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) argument
475 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) argument
476 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) argument
477 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) argument
478 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) argument
479 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) argument
482 * 1:VOL
486 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) argument
487 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) argument
488 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) argument
489 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) argument
492 * 1: FORWARD
495 #define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18)
496 #define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x)) argument
497 #define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0) argument
498 #define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x)) argument
499 #define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0) argument
500 #define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
501 #define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0) argument
528 #define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
529 #define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23) argument
530 #define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28) argument
532 #define PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1
538 #define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0) argument
558 # define FRAME_TMZ (1 << 0)
559 # define FRAME_CMD(x) ((x) << 28) argument
561 * x=0: tmz_begin
562 * x=1: tmz_end
570 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) argument
571 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) argument
572 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) argument
573 # define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) argument
582 /* 1. header
591 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) argument
592 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) argument
593 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) argument
596 /* 1. header
605 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
606 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) argument
607 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) argument
608 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) argument
609 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) argument
610 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) argument
611 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) argument
612 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
613 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
615 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) argument
616 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) argument
618 /* 1. header
626 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) argument
628 * 1 - RESET_QUEUES
632 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
633 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
634 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
636 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) argument
638 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) argument
640 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) argument
642 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) argument
644 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) argument
646 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) argument
648 /* 1. header
657 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) argument
658 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) argument
659 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) argument
661 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) argument
663 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) argument
664 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) argument
669 /* 1. header
675 # define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0) argument
676 # define PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM (1 << 0)