amd/amdgpu/gfx_v11_0.c

55 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
56 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1	0x1388
58 #define regCGTT_WD_CLK_CTRL		0x5086
60 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1	0x4e7e
62 #define regPC_CONFIG_CNTL_1		0x194d
65 #define regCP_GFX_MQD_CONTROL_DEFAULT                                             0x00000100
66 #define regCP_GFX_HQD_VMID_DEFAULT                                                0x00000000
67 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT                                      0x00000000
68 #define regCP_GFX_HQD_QUANTUM_DEFAULT                                             0x00000a01
69 #define regCP_GFX_HQD_CNTL_DEFAULT                                                0x00a00000
70 #define regCP_RB_DOORBELL_CONTROL_DEFAULT                                         0x00000000
71 #define regCP_GFX_HQD_RPTR_DEFAULT                                                0x00000000
73 #define regCP_HQD_EOP_CONTROL_DEFAULT                                             0x00000006
74 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000
75 #define regCP_MQD_CONTROL_DEFAULT                                                 0x00000100
76 #define regCP_HQD_PQ_CONTROL_DEFAULT                                              0x00308509
77 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000
78 #define regCP_HQD_PQ_RPTR_DEFAULT                                                 0x00000000
79 #define regCP_HQD_PERSISTENT_STATE_DEFAULT                                        0x0be05501
80 #define regCP_HQD_IB_CONTROL_DEFAULT                                              0x00300000
122 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
123 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
124 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
125 	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
126 	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
127 	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
128 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
129 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
130 	SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
131 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
132 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
133 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
134 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
135 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
136 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
137 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
138 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
139 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
140 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
141 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
142 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
143 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
144 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
145 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
146 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
147 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
148 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
149 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
150 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
151 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
152 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
153 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
154 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
155 	SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
156 	SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
157 	SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
158 	SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
159 	SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
160 	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
161 	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
162 	SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
163 	SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
164 	SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
165 	SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
166 	SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
167 	SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
168 	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
169 	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
170 	SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
171 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
172 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
173 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
174 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
175 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
176 	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
177 	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
178 	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
180 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
181 	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
182 	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
183 	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
185 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
186 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
187 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
188 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
189 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
190 	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
195 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
196 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
197 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
198 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
199 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
200 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
201 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
202 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
203 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
204 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
205 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
206 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
207 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
208 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
209 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
210 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
211 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
212 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
213 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
214 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
215 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
216 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
217 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
218 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
219 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
220 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
221 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
222 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
223 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
224 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
225 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
226 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
227 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
228 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
229 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
230 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
231 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
232 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
233 	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
238 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
239 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
240 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
241 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
242 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
243 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
244 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
245 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
246 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
247 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
248 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
249 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
250 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
251 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
252 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
253 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
254 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
255 	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
256 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
257 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
258 	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
259 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
260 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
261 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
262 	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
266 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
271 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
272 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
273 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
274 	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
275 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
276 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
277 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
278 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
279 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
323 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |  in gfx11_kiq_set_resources()
324 			  PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */  in gfx11_kiq_set_resources()
325 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */  in gfx11_kiq_set_resources()
330 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */  in gfx11_kiq_set_resources()
331 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */  in gfx11_kiq_set_resources()
339 	uint32_t me = 0, eng_sel = 0;  in gfx11_kiq_map_queues()
344 		eng_sel = 0;  in gfx11_kiq_map_queues()
347 		me = 0;  in gfx11_kiq_map_queues()
359 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/  in gfx11_kiq_map_queues()
360 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_map_queues()
361 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */  in gfx11_kiq_map_queues()
362 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */  in gfx11_kiq_map_queues()
366 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */  in gfx11_kiq_map_queues()
367 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */  in gfx11_kiq_map_queues()
383 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;  in gfx11_kiq_unmap_queues()
385 	if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {  in gfx11_kiq_unmap_queues()
391 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_unmap_queues()
393 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |  in gfx11_kiq_unmap_queues()
404 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
405 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
406 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
415 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;  in gfx11_kiq_query_status()
419 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |  in gfx11_kiq_query_status()
420 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |  in gfx11_kiq_query_status()
422 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_query_status()
453 	adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;  in gfx_v11_0_set_kiq_pm4_funcs()
461 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_init_golden_registers()
462 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_init_golden_registers()
463 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_init_golden_registers()
482 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));  in gfx_v11_0_write_data_to_reg()
484 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_write_data_to_reg()
495 			  /* memory (1) or register (0) */  in gfx_v11_0_wait_reg_mem()
502 		BUG_ON(addr0 & 0x3); /* Dword align */  in gfx_v11_0_wait_reg_mem()
518 	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/  in gfx_v11_ring_insert_nop()
519 	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));  in gfx_v11_ring_insert_nop()
521 	/* Header is at index 0, followed by num_nops - 1 NOP packet's */  in gfx_v11_ring_insert_nop()
528 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);  in gfx_v11_0_ring_test_ring()
529 	uint32_t tmp = 0;  in gfx_v11_0_ring_test_ring()
533 	WREG32(scratch, 0xCAFEDEAD);  in gfx_v11_0_ring_test_ring()
542 		gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);  in gfx_v11_0_ring_test_ring()
547 		amdgpu_ring_write(ring, 0xDEADBEEF);  in gfx_v11_0_ring_test_ring()
551 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_ring_test_ring()
553 		if (tmp == 0xDEADBEEF)  in gfx_v11_0_ring_test_ring()
579 		return 0;  in gfx_v11_0_ring_test_ib()
581 	memset(&ib, 0, sizeof(ib));  in gfx_v11_0_ring_test_ib()
595 		*cpu_ptr = cpu_to_le32(0xCAFEDEAD);  in gfx_v11_0_ring_test_ib()
602 		adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);  in gfx_v11_0_ring_test_ib()
612 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v11_0_ring_test_ib()
616 	ib.ptr[4] = 0xDEADBEEF;  in gfx_v11_0_ring_test_ib()
624 	if (r == 0) {  in gfx_v11_0_ring_test_ib()
627 	} else if (r < 0) {  in gfx_v11_0_ring_test_ib()
631 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)  in gfx_v11_0_ring_test_ib()
632 		r = 0;  in gfx_v11_0_ring_test_ib()
658 	int err = 0;  in gfx_v11_0_init_toc_microcode()
672 	return 0;  in gfx_v11_0_init_toc_microcode()
680 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_check_fw_cp_gfx_shadow()
681 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_check_fw_cp_gfx_shadow()
682 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_check_fw_cp_gfx_shadow()
683 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_check_fw_cp_gfx_shadow()
718 				adev->gfx.pfp_fw->data, 2, 0);  in gfx_v11_0_init_microcode()
742 		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &&  in gfx_v11_0_init_microcode()
743 		    adev->pdev->revision == 0xCE)  in gfx_v11_0_init_microcode()
780 	/* only one MEC for gfx 11.0.0. */  in gfx_v11_0_init_microcode()
805 	u32 count = 0;  in gfx_v11_0_get_csb_size()
819 				return 0;  in gfx_v11_0_get_csb_size()
836 	u32 count = 0, i;  in gfx_v11_0_get_csb_buffer()
846 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_get_csb_buffer()
850 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v11_0_get_csb_buffer()
851 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v11_0_get_csb_buffer()
860 				for (i = 0; i < ext->reg_count; i++)  in gfx_v11_0_get_csb_buffer()
869 		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;  in gfx_v11_0_get_csb_buffer()
874 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_get_csb_buffer()
877 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v11_0_get_csb_buffer()
878 	buffer[count++] = cpu_to_le32(0);  in gfx_v11_0_get_csb_buffer()
898 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];  in gfx_v11_0_init_rlcg_reg_access_ctrl()
899 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
900 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
901 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
902 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
903 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
904 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
905 	reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);  in gfx_v11_0_init_rlcg_reg_access_ctrl()
925 	/* init spm vmid with 0xf */  in gfx_v11_0_rlc_init()
927 		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);  in gfx_v11_0_rlc_init()
929 	return 0;  in gfx_v11_0_rlc_init()
952 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);  in gfx_v11_0_mec_init()
970 		memset(hpd, 0, mec_hpd_size);  in gfx_v11_0_mec_init()
976 	return 0;  in gfx_v11_0_mec_init()
981 	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,  in wave_read_ind()
984 	return RREG32_SOC15(GC, 0, regSQ_IND_DATA);  in wave_read_ind()
991 	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,  in wave_read_regs()
997 		*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);  in wave_read_regs()
1005 	WARN_ON(simd != 0);  in gfx_v11_0_read_wave_data()
1030 	WARN_ON(simd != 0);  in gfx_v11_0_read_wave_sgprs()
1033 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,  in gfx_v11_0_read_wave_sgprs()
1067 		return 0;  in gfx_v11_0_get_gfx_shadow_info()
1069 		memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));  in gfx_v11_0_get_gfx_shadow_info()
1087 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_gpu_early_init()
1088 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_gpu_early_init()
1089 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_gpu_early_init()
1091 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v11_0_gpu_early_init()
1092 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v11_0_gpu_early_init()
1093 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;  in gfx_v11_0_gpu_early_init()
1094 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;  in gfx_v11_0_gpu_early_init()
1096 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_gpu_early_init()
1099 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v11_0_gpu_early_init()
1100 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v11_0_gpu_early_init()
1101 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;  in gfx_v11_0_gpu_early_init()
1102 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;  in gfx_v11_0_gpu_early_init()
1104 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_gpu_early_init()
1105 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_gpu_early_init()
1106 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_gpu_early_init()
1111 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v11_0_gpu_early_init()
1112 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v11_0_gpu_early_init()
1113 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;  in gfx_v11_0_gpu_early_init()
1114 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;  in gfx_v11_0_gpu_early_init()
1121 	return 0;  in gfx_v11_0_gpu_early_init()
1144 	ring->vm_hub = AMDGPU_GFXHUB(0);  in gfx_v11_0_gfx_ring_init()
1174 	ring->vm_hub = AMDGPU_GFXHUB(0);  in gfx_v11_0_compute_ring_init()
1188 	return 0;  in gfx_v11_0_compute_ring_init()
1213 	uint32_t total_size = 0;  in gfx_v11_0_calc_toc_total_size()
1248 	return 0;  in gfx_v11_0_rlc_autoload_buffer_init()
1267 	if (fw_size == 0)  in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1276 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);  in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1289 	*(uint64_t *)fw_autoload_mask |= 0x1;  in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1291 	DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);  in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1438 		adev->sdma.instance[0].fw->data;  in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1439 	fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +  in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1446 	fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +  in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1462 	for (pipe = 0; pipe < 2; pipe++) {  in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1463 		if (pipe==0) {  in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1496 	memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);  in gfx_v11_0_rlc_backdoor_autoload_enable()
1508 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));  in gfx_v11_0_rlc_backdoor_autoload_enable()
1509 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));  in gfx_v11_0_rlc_backdoor_autoload_enable()
1511 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);  in gfx_v11_0_rlc_backdoor_autoload_enable()
1525 	return 0;  in gfx_v11_0_rlc_backdoor_autoload_enable()
1571 	int i, j, k, r, ring_id = 0;  in gfx_v11_0_sw_init()
1572 	int xcc_id = 0;  in gfx_v11_0_sw_init()
1577 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_sw_init()
1578 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_sw_init()
1579 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_sw_init()
1580 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_sw_init()
1588 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_sw_init()
1589 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_sw_init()
1590 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_sw_init()
1611 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_sw_init()
1612 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_sw_init()
1613 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_sw_init()
1614 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_sw_init()
1620 		    adev->mes.fw_version[0] >= 99) {  in gfx_v11_0_sw_init()
1629 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_sw_init()
1634 		    adev->mes.fw_version[0] >= 114) {  in gfx_v11_0_sw_init()
1649 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &&  in gfx_v11_0_sw_init()
1705 	for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_0_sw_init()
1706 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {  in gfx_v11_0_sw_init()
1707 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {  in gfx_v11_0_sw_init()
1720 	ring_id = 0;  in gfx_v11_0_sw_init()
1722 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v11_0_sw_init()
1723 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v11_0_sw_init()
1724 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v11_0_sw_init()
1725 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,  in gfx_v11_0_sw_init()
1740 		amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);  in gfx_v11_0_sw_init()
1742 		amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);  in gfx_v11_0_sw_init()
1743 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_sw_init()
1744 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_sw_init()
1745 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_sw_init()
1746 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_sw_init()
1758 		r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);  in gfx_v11_0_sw_init()
1769 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0);  in gfx_v11_0_sw_init()
1795 	return 0;  in gfx_v11_0_sw_init()
1832 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v11_0_sw_fini()
1834 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v11_0_sw_fini()
1837 	amdgpu_gfx_mqd_sw_fini(adev, 0);  in gfx_v11_0_sw_fini()
1840 		amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);  in gfx_v11_0_sw_fini()
1841 		amdgpu_gfx_kiq_fini(adev, 0);  in gfx_v11_0_sw_fini()
1862 	return 0;  in gfx_v11_0_sw_fini()
1870 	if (instance == 0xffffffff)  in gfx_v11_0_select_se_sh()
1871 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,  in gfx_v11_0_select_se_sh()
1874 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,  in gfx_v11_0_select_se_sh()
1877 	if (se_num == 0xffffffff)  in gfx_v11_0_select_se_sh()
1883 	if (sh_num == 0xffffffff)  in gfx_v11_0_select_se_sh()
1889 	WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);  in gfx_v11_0_select_se_sh()
1896 	gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);  in gfx_v11_0_get_sa_active_bitmap()
1900 	gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);  in gfx_v11_0_get_sa_active_bitmap()
1915 	gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);  in gfx_v11_0_get_rb_active_bitmap()
1919 	gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);  in gfx_v11_0_get_rb_active_bitmap()
1936 	u32 active_rb_bitmap = 0;  in gfx_v11_0_setup_rb()
1951 	for (i = 0; i < max_sa; i++) {  in gfx_v11_0_setup_rb()
1961 #define DEFAULT_SH_MEM_BASES	(0x6000)
1962 #define LDS_APP_BASE           0x1
1963 #define SCRATCH_APP_BASE       0x2
1973 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)  in gfx_v11_0_init_compute_vmid()
1974 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)  in gfx_v11_0_init_compute_vmid()
1975 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)  in gfx_v11_0_init_compute_vmid()
1982 		soc21_grbm_select(adev, 0, 0, 0, i);  in gfx_v11_0_init_compute_vmid()
1984 		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);  in gfx_v11_0_init_compute_vmid()
1985 		WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);  in gfx_v11_0_init_compute_vmid()
1988 		data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);  in gfx_v11_0_init_compute_vmid()
1990 		WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);  in gfx_v11_0_init_compute_vmid()
1992 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_init_compute_vmid()
2000 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);  in gfx_v11_0_init_compute_vmid()
2001 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);  in gfx_v11_0_init_compute_vmid()
2002 		WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);  in gfx_v11_0_init_compute_vmid()
2003 		WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);  in gfx_v11_0_init_compute_vmid()
2018 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);  in gfx_v11_0_init_gds_vmid()
2019 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);  in gfx_v11_0_init_gds_vmid()
2020 		WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);  in gfx_v11_0_init_gds_vmid()
2021 		WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);  in gfx_v11_0_init_gds_vmid()
2033 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |  in gfx_v11_0_get_tcc_info()
2034 			       RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);  in gfx_v11_0_get_tcc_info()
2047 		WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);  in gfx_v11_0_constants_init()
2052 	adev->gfx.config.pa_sc_tile_steering_override = 0;  in gfx_v11_0_constants_init()
2055 	tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);  in gfx_v11_0_constants_init()
2062 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {  in gfx_v11_0_constants_init()
2063 		soc21_grbm_select(adev, 0, 0, 0, i);  in gfx_v11_0_constants_init()
2065 		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);  in gfx_v11_0_constants_init()
2066 		if (i != 0) {  in gfx_v11_0_constants_init()
2067 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,  in gfx_v11_0_constants_init()
2071 			WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);  in gfx_v11_0_constants_init()
2074 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_constants_init()
2085 	if (me != 0)  in gfx_v11_0_get_cpg_int_cntl()
2086 		return 0;  in gfx_v11_0_get_cpg_int_cntl()
2089 	case 0:  in gfx_v11_0_get_cpg_int_cntl()
2090 		return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);  in gfx_v11_0_get_cpg_int_cntl()
2092 		return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);  in gfx_v11_0_get_cpg_int_cntl()
2094 		return 0;  in gfx_v11_0_get_cpg_int_cntl()
2107 		return 0;  in gfx_v11_0_get_cpc_int_cntl()
2110 	case 0:  in gfx_v11_0_get_cpc_int_cntl()
2111 		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);  in gfx_v11_0_get_cpc_int_cntl()
2113 		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);  in gfx_v11_0_get_cpc_int_cntl()
2115 		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);  in gfx_v11_0_get_cpc_int_cntl()
2117 		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);  in gfx_v11_0_get_cpc_int_cntl()
2119 		return 0;  in gfx_v11_0_get_cpc_int_cntl()
2132 	for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_0_enable_gui_idle_interrupt()
2133 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {  in gfx_v11_0_enable_gui_idle_interrupt()
2139 						    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
2141 						    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
2143 						    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
2145 						    enable ? 1 : 0);  in gfx_v11_0_enable_gui_idle_interrupt()
2156 	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,  in gfx_v11_0_init_csb()
2158 	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,  in gfx_v11_0_init_csb()
2159 			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);  in gfx_v11_0_init_csb()
2160 	WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);  in gfx_v11_0_init_csb()
2162 	return 0;  in gfx_v11_0_init_csb()
2167 	u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);  in gfx_v11_0_rlc_stop()
2169 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);  in gfx_v11_0_rlc_stop()
2170 	WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);  in gfx_v11_0_rlc_stop()
2175 	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);  in gfx_v11_0_rlc_reset()
2177 	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);  in gfx_v11_0_rlc_reset()
2186 	rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);  in gfx_v11_0_rlc_smu_handshake_cntl()
2189 		/* RLC_PG_CNTL[23] = 0 (default)  in gfx_v11_0_rlc_smu_handshake_cntl()
2200 	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);  in gfx_v11_0_rlc_smu_handshake_cntl()
2210 	WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);  in gfx_v11_0_rlc_start()
2219 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));  in gfx_v11_0_rlc_enable_srm()
2222 	WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);  in gfx_v11_0_rlc_enable_srm()
2236 	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,  in gfx_v11_0_load_rlcg_microcode()
2239 	for (i = 0; i < fw_size; i++)  in gfx_v11_0_load_rlcg_microcode()
2240 		WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,  in gfx_v11_0_load_rlcg_microcode()
2243 	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlcg_microcode()
2259 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2261 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlc_iram_dram_microcode()
2264 		WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,  in gfx_v11_0_load_rlc_iram_dram_microcode()
2268 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2274 	WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2275 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlc_iram_dram_microcode()
2278 		WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,  in gfx_v11_0_load_rlc_iram_dram_microcode()
2282 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2284 	tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2286 	tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2287 	WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);  in gfx_v11_0_load_rlc_iram_dram_microcode()
2303 	WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2305 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlcp_rlcv_microcode()
2308 		WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,  in gfx_v11_0_load_rlcp_rlcv_microcode()
2312 	WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2314 	tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2316 	WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2322 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2324 	for (i = 0; i < fw_size; i++) {  in gfx_v11_0_load_rlcp_rlcv_microcode()
2327 		WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,  in gfx_v11_0_load_rlcp_rlcv_microcode()
2331 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2333 	tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2335 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);  in gfx_v11_0_load_rlcp_rlcv_microcode()
2362 		return 0;  in gfx_v11_0_rlc_load_microcode()
2380 			return 0;  in gfx_v11_0_rlc_resume()
2386 		WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);  in gfx_v11_0_rlc_resume()
2389 		WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);  in gfx_v11_0_rlc_resume()
2402 	return 0;  in gfx_v11_0_rlc_resume()
2412 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache()
2414 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);  in gfx_v11_0_config_me_cache()
2417 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache()
2418 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache()
2433 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);  in gfx_v11_0_config_me_cache()
2434 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache()
2435 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_me_cache()
2436 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_me_cache()
2438 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_me_cache()
2441 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,  in gfx_v11_0_config_me_cache()
2442 			lower_32_bits(addr) & 0xFFFFF000);  in gfx_v11_0_config_me_cache()
2443 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,  in gfx_v11_0_config_me_cache()
2446 	return 0;  in gfx_v11_0_config_me_cache()
2456 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache()
2458 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);  in gfx_v11_0_config_pfp_cache()
2461 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache()
2462 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache()
2477 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);  in gfx_v11_0_config_pfp_cache()
2478 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache()
2479 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_pfp_cache()
2480 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_pfp_cache()
2482 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_pfp_cache()
2485 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,  in gfx_v11_0_config_pfp_cache()
2486 			lower_32_bits(addr) & 0xFFFFF000);  in gfx_v11_0_config_pfp_cache()
2487 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,  in gfx_v11_0_config_pfp_cache()
2490 	return 0;  in gfx_v11_0_config_pfp_cache()
2500 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache()
2503 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);  in gfx_v11_0_config_mec_cache()
2506 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_mec_cache()
2507 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache()
2522 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);  in gfx_v11_0_config_mec_cache()
2523 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_mec_cache()
2524 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_mec_cache()
2526 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_mec_cache()
2529 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,  in gfx_v11_0_config_mec_cache()
2530 			lower_32_bits(addr) & 0xFFFFF000);  in gfx_v11_0_config_mec_cache()
2531 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,  in gfx_v11_0_config_mec_cache()
2534 	return 0;  in gfx_v11_0_config_mec_cache()
2547 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,  in gfx_v11_0_config_pfp_cache_rs64()
2549 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,  in gfx_v11_0_config_pfp_cache_rs64()
2552 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2553 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2554 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2555 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2556 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2563 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache_rs64()
2564 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2577 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2579 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2581 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache_rs64()
2582 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2595 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_config_pfp_cache_rs64()
2596 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2597 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,  in gfx_v11_0_config_pfp_cache_rs64()
2600 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_pfp_cache_rs64()
2607 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2608 		if (pipe_id == 0)  in gfx_v11_0_config_pfp_cache_rs64()
2614 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2617 		if (pipe_id == 0)  in gfx_v11_0_config_pfp_cache_rs64()
2619 					PFP_PIPE0_RESET, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2622 					PFP_PIPE1_RESET, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2623 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2625 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,  in gfx_v11_0_config_pfp_cache_rs64()
2627 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,  in gfx_v11_0_config_pfp_cache_rs64()
2630 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2633 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2634 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2635 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2636 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2639 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2641 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_config_pfp_cache_rs64()
2643 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_pfp_cache_rs64()
2644 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_pfp_cache_rs64()
2656 	return 0;  in gfx_v11_0_config_pfp_cache_rs64()
2669 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,  in gfx_v11_0_config_me_cache_rs64()
2671 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,  in gfx_v11_0_config_me_cache_rs64()
2674 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2675 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2676 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_me_cache_rs64()
2677 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_me_cache_rs64()
2678 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2685 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache_rs64()
2686 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2699 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2701 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2704 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache_rs64()
2705 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2718 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_config_me_cache_rs64()
2719 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_me_cache_rs64()
2720 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,  in gfx_v11_0_config_me_cache_rs64()
2723 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_me_cache_rs64()
2730 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2731 		if (pipe_id == 0)  in gfx_v11_0_config_me_cache_rs64()
2737 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2740 		if (pipe_id == 0)  in gfx_v11_0_config_me_cache_rs64()
2742 					ME_PIPE0_RESET, 0);  in gfx_v11_0_config_me_cache_rs64()
2745 					ME_PIPE1_RESET, 0);  in gfx_v11_0_config_me_cache_rs64()
2746 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2748 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,  in gfx_v11_0_config_me_cache_rs64()
2750 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,  in gfx_v11_0_config_me_cache_rs64()
2753 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_me_cache_rs64()
2756 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2757 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2758 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_me_cache_rs64()
2759 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2762 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2764 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_config_me_cache_rs64()
2766 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_me_cache_rs64()
2767 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_config_me_cache_rs64()
2779 	return 0;  in gfx_v11_0_config_me_cache_rs64()
2792 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2793 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2794 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_config_mec_cache_rs64()
2795 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_mec_cache_rs64()
2796 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2798 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2799 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2800 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_config_mec_cache_rs64()
2801 	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2804 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {  in gfx_v11_0_config_mec_cache_rs64()
2805 		soc21_grbm_select(adev, 1, i, 0, 0);  in gfx_v11_0_config_mec_cache_rs64()
2807 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);  in gfx_v11_0_config_mec_cache_rs64()
2808 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,  in gfx_v11_0_config_mec_cache_rs64()
2811 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,  in gfx_v11_0_config_mec_cache_rs64()
2814 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_mec_cache_rs64()
2817 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);  in gfx_v11_0_config_mec_cache_rs64()
2818 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,  in gfx_v11_0_config_mec_cache_rs64()
2822 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_mec_cache_rs64()
2825 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2827 	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2830 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_mec_cache_rs64()
2831 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2844 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2846 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);  in gfx_v11_0_config_mec_cache_rs64()
2849 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_config_mec_cache_rs64()
2850 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_config_mec_cache_rs64()
2862 	return 0;  in gfx_v11_0_config_mec_cache_rs64()
2880 	for (pipe_id = 0; pipe_id < 2; pipe_id++) {  in gfx_v11_0_config_gfx_rs64()
2881 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2882 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,  in gfx_v11_0_config_gfx_rs64()
2885 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_gfx_rs64()
2888 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2891 	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_gfx_rs64()
2894 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2897 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2898 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2899 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2902 	for (pipe_id = 0; pipe_id < 2; pipe_id++) {  in gfx_v11_0_config_gfx_rs64()
2903 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2904 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,  in gfx_v11_0_config_gfx_rs64()
2907 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_gfx_rs64()
2910 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2913 	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_config_gfx_rs64()
2916 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2919 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2920 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2921 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2924 	for (pipe_id = 0; pipe_id < 4; pipe_id++) {  in gfx_v11_0_config_gfx_rs64()
2925 		soc21_grbm_select(adev, 1, pipe_id, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2926 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,  in gfx_v11_0_config_gfx_rs64()
2929 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,  in gfx_v11_0_config_gfx_rs64()
2932 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_config_gfx_rs64()
2935 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);  in gfx_v11_0_config_gfx_rs64()
2940 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2943 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2944 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2945 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2946 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);  in gfx_v11_0_config_gfx_rs64()
2947 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);  in gfx_v11_0_config_gfx_rs64()
2957 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_wait_for_rlc_autoload_complete()
2958 		cp_status = RREG32_SOC15(GC, 0, regCP_STAT);  in gfx_v11_0_wait_for_rlc_autoload_complete()
2960 		if (amdgpu_ip_version(adev, GC_HWIP, 0) ==  in gfx_v11_0_wait_for_rlc_autoload_complete()
2961 			    IP_VERSION(11, 0, 1) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2962 		    amdgpu_ip_version(adev, GC_HWIP, 0) ==  in gfx_v11_0_wait_for_rlc_autoload_complete()
2963 			    IP_VERSION(11, 0, 4) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2964 		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2965 		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2966 		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) ||  in gfx_v11_0_wait_for_rlc_autoload_complete()
2967 		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3))  in gfx_v11_0_wait_for_rlc_autoload_complete()
2968 			bootload_status = RREG32_SOC15(GC, 0,  in gfx_v11_0_wait_for_rlc_autoload_complete()
2971 			bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);  in gfx_v11_0_wait_for_rlc_autoload_complete()
2973 		if ((cp_status == 0) &&  in gfx_v11_0_wait_for_rlc_autoload_complete()
3028 	return 0;  in gfx_v11_0_wait_for_rlc_autoload_complete()
3034 	u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_cp_gfx_enable()
3036 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);  in gfx_v11_0_cp_gfx_enable()
3037 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);  in gfx_v11_0_cp_gfx_enable()
3038 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_enable()
3040 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_cp_gfx_enable()
3041 		if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)  in gfx_v11_0_cp_gfx_enable()
3049 	return 0;  in gfx_v11_0_cp_gfx_enable()
3086 	WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode()
3088 	for (i = 0; i < pfp_hdr->jt_size; i++)  in gfx_v11_0_cp_gfx_load_pfp_microcode()
3089 		WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,  in gfx_v11_0_cp_gfx_load_pfp_microcode()
3092 	WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);  in gfx_v11_0_cp_gfx_load_pfp_microcode()
3094 	return 0;  in gfx_v11_0_cp_gfx_load_pfp_microcode()
3158 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3160 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3163 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3164 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3165 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3166 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3167 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3174 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3175 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3188 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3190 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3192 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3193 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3206 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3207 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3208 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3211 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3218 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3219 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3225 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3228 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3230 					PFP_PIPE0_RESET, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3233 					PFP_PIPE1_RESET, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3234 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3236 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3238 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3241 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3244 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3245 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3246 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3247 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3250 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3252 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3254 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3255 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3267 	return 0;  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3304 	WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);  in gfx_v11_0_cp_gfx_load_me_microcode()
3306 	for (i = 0; i < me_hdr->jt_size; i++)  in gfx_v11_0_cp_gfx_load_me_microcode()
3307 		WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,  in gfx_v11_0_cp_gfx_load_me_microcode()
3310 	WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);  in gfx_v11_0_cp_gfx_load_me_microcode()
3312 	return 0;  in gfx_v11_0_cp_gfx_load_me_microcode()
3376 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3378 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3381 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3382 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3383 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3384 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3385 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3392 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3393 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3406 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3408 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3411 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3412 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3425 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3426 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3427 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3430 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3437 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3438 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3444 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3447 		if (pipe_id == 0)  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3449 					ME_PIPE0_RESET, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3452 					ME_PIPE1_RESET, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3453 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3455 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3457 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3460 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3463 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3464 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3465 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3466 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3469 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3471 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3473 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3474 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3486 	return 0;  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3516 	return 0;  in gfx_v11_0_cp_gfx_load_microcode()
3528 	WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,  in gfx_v11_0_cp_gfx_start()
3530 	WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);  in gfx_v11_0_cp_gfx_start()
3535 	ring = &adev->gfx.gfx_ring[0];  in gfx_v11_0_cp_gfx_start()
3542 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_cp_gfx_start()
3546 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v11_0_cp_gfx_start()
3547 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v11_0_cp_gfx_start()
3557 				for (i = 0; i < ext->reg_count; i++)  in gfx_v11_0_cp_gfx_start()
3564 		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;  in gfx_v11_0_cp_gfx_start()
3569 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v11_0_cp_gfx_start()
3572 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v11_0_cp_gfx_start()
3573 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_cp_gfx_start()
3577 	/* submit cs packet to copy state 0 to next available state */  in gfx_v11_0_cp_gfx_start()
3587 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v11_0_cp_gfx_start()
3588 		amdgpu_ring_write(ring, 0);  in gfx_v11_0_cp_gfx_start()
3592 	return 0;  in gfx_v11_0_cp_gfx_start()
3600 	tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);  in gfx_v11_0_cp_gfx_switch_pipe()
3603 	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);  in gfx_v11_0_cp_gfx_switch_pipe()
3611 	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);  in gfx_v11_0_cp_gfx_set_doorbell()
3619 				    DOORBELL_EN, 0);  in gfx_v11_0_cp_gfx_set_doorbell()
3621 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);  in gfx_v11_0_cp_gfx_set_doorbell()
3623 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,  in gfx_v11_0_cp_gfx_set_doorbell()
3625 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);  in gfx_v11_0_cp_gfx_set_doorbell()
3627 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,  in gfx_v11_0_cp_gfx_set_doorbell()
3639 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);  in gfx_v11_0_cp_gfx_resume()
3641 	/* set the RB to use vmid 0 */  in gfx_v11_0_cp_gfx_resume()
3642 	WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);  in gfx_v11_0_cp_gfx_resume()
3644 	/* Init gfx ring 0 for pipe 0 */  in gfx_v11_0_cp_gfx_resume()
3649 	ring = &adev->gfx.gfx_ring[0];  in gfx_v11_0_cp_gfx_resume()
3651 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);  in gfx_v11_0_cp_gfx_resume()
3653 	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3656 	ring->wptr = 0;  in gfx_v11_0_cp_gfx_resume()
3657 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3658 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3662 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));  in gfx_v11_0_cp_gfx_resume()
3663 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &  in gfx_v11_0_cp_gfx_resume()
3667 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,  in gfx_v11_0_cp_gfx_resume()
3669 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,  in gfx_v11_0_cp_gfx_resume()
3673 	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3676 	WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);  in gfx_v11_0_cp_gfx_resume()
3677 	WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));  in gfx_v11_0_cp_gfx_resume()
3679 	WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);  in gfx_v11_0_cp_gfx_resume()
3691 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);  in gfx_v11_0_cp_gfx_resume()
3693 		WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3695 		ring->wptr = 0;  in gfx_v11_0_cp_gfx_resume()
3696 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3697 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));  in gfx_v11_0_cp_gfx_resume()
3700 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));  in gfx_v11_0_cp_gfx_resume()
3701 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &  in gfx_v11_0_cp_gfx_resume()
3704 		WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,  in gfx_v11_0_cp_gfx_resume()
3706 		WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,  in gfx_v11_0_cp_gfx_resume()
3710 		WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);  in gfx_v11_0_cp_gfx_resume()
3713 		WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);  in gfx_v11_0_cp_gfx_resume()
3714 		WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));  in gfx_v11_0_cp_gfx_resume()
3715 		WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);  in gfx_v11_0_cp_gfx_resume()
3720 	/* Switch to pipe 0 */  in gfx_v11_0_cp_gfx_resume()
3728 	return 0;  in gfx_v11_0_cp_gfx_resume()
3736 		data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);  in gfx_v11_0_cp_compute_enable()
3738 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3740 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3742 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3744 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3746 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3748 							 enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3750 				                         enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3752 							 enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3754 							 enable ? 1 : 0);  in gfx_v11_0_cp_compute_enable()
3756 							 enable ? 0 : 1);  in gfx_v11_0_cp_compute_enable()
3757 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);  in gfx_v11_0_cp_compute_enable()
3759 		data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);  in gfx_v11_0_cp_compute_enable()
3762 			data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);  in gfx_v11_0_cp_compute_enable()
3765 						     MEC_ME2_HALT, 0);  in gfx_v11_0_cp_compute_enable()
3770 		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);  in gfx_v11_0_cp_compute_enable()
3816 	WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);  in gfx_v11_0_cp_compute_load_microcode()
3818 	for (i = 0; i < mec_hdr->jt_size; i++)  in gfx_v11_0_cp_compute_load_microcode()
3819 		WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,  in gfx_v11_0_cp_compute_load_microcode()
3822 	WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);  in gfx_v11_0_cp_compute_load_microcode()
3824 	return 0;  in gfx_v11_0_cp_compute_load_microcode()
3886 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3887 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3888 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3889 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3890 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3892 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3893 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3894 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3895 	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3898 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {  in gfx_v11_0_cp_compute_load_microcode_rs64()
3899 		soc21_grbm_select(adev, 1, i, 0, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3901 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3902 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3905 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3908 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3911 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3912 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,  in gfx_v11_0_cp_compute_load_microcode_rs64()
3916 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3919 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3921 	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3924 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_compute_load_microcode_rs64()
3925 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3938 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3940 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3943 	for (i = 0; i < usec_timeout; i++) {  in gfx_v11_0_cp_compute_load_microcode_rs64()
3944 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3956 	return 0;  in gfx_v11_0_cp_compute_load_microcode_rs64()
3965 	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);  in gfx_v11_0_kiq_setting()
3966 	tmp &= 0xffffff00;  in gfx_v11_0_kiq_setting()
3968 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);  in gfx_v11_0_kiq_setting()
3974 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,  in gfx_v11_0_cp_set_doorbell_range()
3976 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,  in gfx_v11_0_cp_set_doorbell_range()
3980 	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,  in gfx_v11_0_cp_set_doorbell_range()
3982 	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,  in gfx_v11_0_cp_set_doorbell_range()
3990 	bool priority = 0;  in gfx_v11_0_gfx_mqd_set_priority()
3994 	 * 0x0 = low priority, 0x1 = high priority  in gfx_v11_0_gfx_mqd_set_priority()
4013 	mqd->cp_gfx_hqd_wptr = 0;  in gfx_v11_0_gfx_mqd_init()
4014 	mqd->cp_gfx_hqd_wptr_hi = 0;  in gfx_v11_0_gfx_mqd_init()
4017 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;  in gfx_v11_0_gfx_mqd_init()
4022 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
4024 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);  in gfx_v11_0_gfx_mqd_init()
4027 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */  in gfx_v11_0_gfx_mqd_init()
4029 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
4030 	mqd->cp_gfx_hqd_vmid = 0;  in gfx_v11_0_gfx_mqd_init()
4047 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_gfx_mqd_init()
4049 		upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_gfx_mqd_init()
4053 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_gfx_mqd_init()
4054 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_gfx_mqd_init()
4075 				    DOORBELL_EN, 0);  in gfx_v11_0_gfx_mqd_init()
4084 	return 0;  in gfx_v11_0_gfx_mqd_init()
4091 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];  in gfx_v11_0_kgq_init_queue()
4094 		memset((void *)mqd, 0, sizeof(*mqd));  in gfx_v11_0_kgq_init_queue()
4096 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kgq_init_queue()
4098 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kgq_init_queue()
4107 		ring->wptr = 0;  in gfx_v11_0_kgq_init_queue()
4108 		*ring->wptr_cpu_addr = 0;  in gfx_v11_0_kgq_init_queue()
4112 	return 0;  in gfx_v11_0_kgq_init_queue()
4119 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_cp_async_gfx_ring_resume()
4125 	r = amdgpu_gfx_enable_kgq(adev, 0);  in gfx_v11_0_cp_async_gfx_ring_resume()
4139 	mqd->header = 0xC0310800;  in gfx_v11_0_compute_mqd_init()
4140 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v11_0_compute_mqd_init()
4141 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
4142 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
4143 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
4144 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v11_0_compute_mqd_init()
4145 	mqd->compute_misc_reserved = 0x00000007;  in gfx_v11_0_compute_mqd_init()
4167 				    DOORBELL_SOURCE, 0);  in gfx_v11_0_compute_mqd_init()
4169 				    DOORBELL_HIT, 0);  in gfx_v11_0_compute_mqd_init()
4172 				    DOORBELL_EN, 0);  in gfx_v11_0_compute_mqd_init()
4178 	mqd->cp_hqd_dequeue_request = 0;  in gfx_v11_0_compute_mqd_init()
4179 	mqd->cp_hqd_pq_rptr = 0;  in gfx_v11_0_compute_mqd_init()
4180 	mqd->cp_hqd_pq_wptr_lo = 0;  in gfx_v11_0_compute_mqd_init()
4181 	mqd->cp_hqd_pq_wptr_hi = 0;  in gfx_v11_0_compute_mqd_init()
4184 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;  in gfx_v11_0_compute_mqd_init()
4187 	/* set MQD vmid to 0 */  in gfx_v11_0_compute_mqd_init()
4189 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);  in gfx_v11_0_compute_mqd_init()
4212 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_compute_mqd_init()
4214 		upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_compute_mqd_init()
4218 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v11_0_compute_mqd_init()
4219 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v11_0_compute_mqd_init()
4221 	tmp = 0;  in gfx_v11_0_compute_mqd_init()
4231 				    DOORBELL_SOURCE, 0);  in gfx_v11_0_compute_mqd_init()
4233 				    DOORBELL_HIT, 0);  in gfx_v11_0_compute_mqd_init()
4242 	mqd->cp_hqd_vmid = 0;  in gfx_v11_0_compute_mqd_init()
4245 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);  in gfx_v11_0_compute_mqd_init()
4259 	return 0;  in gfx_v11_0_compute_mqd_init()
4270 		WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);  in gfx_v11_0_kiq_init_register()
4273 	WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);  in gfx_v11_0_kiq_init_register()
4276 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,  in gfx_v11_0_kiq_init_register()
4278 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,  in gfx_v11_0_kiq_init_register()
4282 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,  in gfx_v11_0_kiq_init_register()
4286 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,  in gfx_v11_0_kiq_init_register()
4290 	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {  in gfx_v11_0_kiq_init_register()
4291 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);  in gfx_v11_0_kiq_init_register()
4292 		for (j = 0; j < adev->usec_timeout; j++) {  in gfx_v11_0_kiq_init_register()
4293 			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))  in gfx_v11_0_kiq_init_register()
4297 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,  in gfx_v11_0_kiq_init_register()
4299 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,  in gfx_v11_0_kiq_init_register()
4301 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,  in gfx_v11_0_kiq_init_register()
4303 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,  in gfx_v11_0_kiq_init_register()
4308 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,  in gfx_v11_0_kiq_init_register()
4310 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,  in gfx_v11_0_kiq_init_register()
4313 	/* set MQD vmid to 0 */  in gfx_v11_0_kiq_init_register()
4314 	WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,  in gfx_v11_0_kiq_init_register()
4318 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,  in gfx_v11_0_kiq_init_register()
4320 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,  in gfx_v11_0_kiq_init_register()
4324 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,  in gfx_v11_0_kiq_init_register()
4328 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,  in gfx_v11_0_kiq_init_register()
4330 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,  in gfx_v11_0_kiq_init_register()
4334 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,  in gfx_v11_0_kiq_init_register()
4336 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,  in gfx_v11_0_kiq_init_register()
4341 		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,  in gfx_v11_0_kiq_init_register()
4343 		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,  in gfx_v11_0_kiq_init_register()
4347 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,  in gfx_v11_0_kiq_init_register()
4351 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,  in gfx_v11_0_kiq_init_register()
4353 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,  in gfx_v11_0_kiq_init_register()
4357 	WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);  in gfx_v11_0_kiq_init_register()
4359 	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,  in gfx_v11_0_kiq_init_register()
4363 	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,  in gfx_v11_0_kiq_init_register()
4367 		WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);  in gfx_v11_0_kiq_init_register()
4369 	return 0;  in gfx_v11_0_kiq_init_register()
4381 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v11_0_kiq_init_queue()
4382 			memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));  in gfx_v11_0_kiq_init_queue()
4385 		ring->wptr = 0;  in gfx_v11_0_kiq_init_queue()
4389 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kiq_init_queue()
4391 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kiq_init_queue()
4394 		memset((void *)mqd, 0, sizeof(*mqd));  in gfx_v11_0_kiq_init_queue()
4398 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kiq_init_queue()
4401 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kiq_init_queue()
4404 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v11_0_kiq_init_queue()
4405 			memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));  in gfx_v11_0_kiq_init_queue()
4408 	return 0;  in gfx_v11_0_kiq_init_queue()
4415 	int mqd_idx = ring - &adev->gfx.compute_ring[0];  in gfx_v11_0_kcq_init_queue()
4418 		memset((void *)mqd, 0, sizeof(*mqd));  in gfx_v11_0_kcq_init_queue()
4420 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v11_0_kcq_init_queue()
4422 		soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_kcq_init_queue()
4432 		ring->wptr = 0;  in gfx_v11_0_kcq_init_queue()
4433 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);  in gfx_v11_0_kcq_init_queue()
4437 	return 0;  in gfx_v11_0_kcq_init_queue()
4442 	gfx_v11_0_kiq_init_queue(&adev->gfx.kiq[0].ring);  in gfx_v11_0_kiq_resume()
4443 	return 0;  in gfx_v11_0_kiq_resume()
4453 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_kcq_resume()
4459 	return amdgpu_gfx_enable_kcq(adev, 0);  in gfx_v11_0_kcq_resume()
4512 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_cp_resume()
4519 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_cp_resume()
4526 	return 0;  in gfx_v11_0_cp_resume()
4552 	adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);  in gfx_v11_0_gfxhub_enable()
4554 	return 0;  in gfx_v11_0_gfxhub_enable()
4563 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);  in gfx_v11_0_select_cp_fw_arch()
4565 		WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);  in gfx_v11_0_select_cp_fw_arch()
4567 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);  in gfx_v11_0_select_cp_fw_arch()
4569 		WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);  in gfx_v11_0_select_cp_fw_arch()
4580 	gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);  in get_gb_addr_config()
4581 	if (gb_addr_config == 0)  in get_gb_addr_config()
4609 	return 0;  in get_gb_addr_config()
4616 	data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);  in gfx_v11_0_disable_gpa_mode()
4618 	WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);  in gfx_v11_0_disable_gpa_mode()
4620 	data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);  in gfx_v11_0_disable_gpa_mode()
4622 	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);  in gfx_v11_0_disable_gpa_mode()
4645 			if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {  in gfx_v11_0_hw_init()
4720 		adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);  in gfx_v11_0_hw_init()
4731 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v11_0_hw_fini()
4732 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v11_0_hw_fini()
4733 	amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);  in gfx_v11_0_hw_fini()
4737 			if (amdgpu_gfx_disable_kgq(adev, 0))  in gfx_v11_0_hw_fini()
4741 		if (amdgpu_gfx_disable_kcq(adev, 0))  in gfx_v11_0_hw_fini()
4753 		return 0;  in gfx_v11_0_hw_fini()
4762 	return 0;  in gfx_v11_0_hw_fini()
4779 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),  in gfx_v11_0_is_idle()
4792 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_wait_for_idle()
4794 		tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &  in gfx_v11_0_wait_for_idle()
4798 			return 0;  in gfx_v11_0_wait_for_idle()
4809 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_request_gfx_index_mutex()
4810 		/* Request with MeId=2, PipeId=0 */  in gfx_v11_0_request_gfx_index_mutex()
4811 		tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);  in gfx_v11_0_request_gfx_index_mutex()
4813 		WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);  in gfx_v11_0_request_gfx_index_mutex()
4815 		val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);  in gfx_v11_0_request_gfx_index_mutex()
4833 	return 0;  in gfx_v11_0_request_gfx_index_mutex()
4838 	u32 grbm_soft_reset = 0;  in gfx_v11_0_soft_reset()
4843 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v11_0_soft_reset()
4845 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);  in gfx_v11_0_soft_reset()
4846 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4847 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4848 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4849 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);  in gfx_v11_0_soft_reset()
4850 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);  in gfx_v11_0_soft_reset()
4853 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v11_0_soft_reset()
4854 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v11_0_soft_reset()
4855 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v11_0_soft_reset()
4856 				soc21_grbm_select(adev, i, k, j, 0);  in gfx_v11_0_soft_reset()
4858 				WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);  in gfx_v11_0_soft_reset()
4859 				WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);  in gfx_v11_0_soft_reset()
4863 	for (i = 0; i < adev->gfx.me.num_me; ++i) {  in gfx_v11_0_soft_reset()
4864 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {  in gfx_v11_0_soft_reset()
4865 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {  in gfx_v11_0_soft_reset()
4866 				soc21_grbm_select(adev, i, k, j, 0);  in gfx_v11_0_soft_reset()
4868 				WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);  in gfx_v11_0_soft_reset()
4872 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_0_soft_reset()
4884 	WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);  in gfx_v11_0_soft_reset()
4887 	// to get sufficient time for GFX_HQD_ACTIVE reach 0  in gfx_v11_0_soft_reset()
4888 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);  in gfx_v11_0_soft_reset()
4889 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);  in gfx_v11_0_soft_reset()
4890 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);  in gfx_v11_0_soft_reset()
4900 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_soft_reset()
4901 		if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&  in gfx_v11_0_soft_reset()
4902 		    !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))  in gfx_v11_0_soft_reset()
4912 	grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in gfx_v11_0_soft_reset()
4923 	WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);  in gfx_v11_0_soft_reset()
4925 	grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in gfx_v11_0_soft_reset()
4927 					SOFT_RESET_CP, 0);  in gfx_v11_0_soft_reset()
4929 					SOFT_RESET_GFX, 0);  in gfx_v11_0_soft_reset()
4931 					SOFT_RESET_CPF, 0);  in gfx_v11_0_soft_reset()
4933 					SOFT_RESET_CPC, 0);  in gfx_v11_0_soft_reset()
4935 					SOFT_RESET_CPG, 0);  in gfx_v11_0_soft_reset()
4936 	WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);  in gfx_v11_0_soft_reset()
4938 	tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);  in gfx_v11_0_soft_reset()
4939 	tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);  in gfx_v11_0_soft_reset()
4940 	WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);  in gfx_v11_0_soft_reset()
4942 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);  in gfx_v11_0_soft_reset()
4943 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);  in gfx_v11_0_soft_reset()
4945 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_soft_reset()
4946 		if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))  in gfx_v11_0_soft_reset()
4951 		printk("Failed to wait CP_VMID_RESET to 0\n");  in gfx_v11_0_soft_reset()
4955 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);  in gfx_v11_0_soft_reset()
4960 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);  in gfx_v11_0_soft_reset()
4962 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v11_0_soft_reset()
4974 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_check_soft_reset()
4981 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_check_soft_reset()
5008 		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);  in gfx_v11_0_get_gpu_clock_counter()
5009 		clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);  in gfx_v11_0_get_gpu_clock_counter()
5010 		clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);  in gfx_v11_0_get_gpu_clock_counter()
5012 			clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);  in gfx_v11_0_get_gpu_clock_counter()
5017 		clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);  in gfx_v11_0_get_gpu_clock_counter()
5018 		clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);  in gfx_v11_0_get_gpu_clock_counter()
5019 		clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);  in gfx_v11_0_get_gpu_clock_counter()
5021 			clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);  in gfx_v11_0_get_gpu_clock_counter()
5038 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
5039 				    SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,  in gfx_v11_0_ring_emit_gds_switch()
5043 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
5044 				    SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,  in gfx_v11_0_ring_emit_gds_switch()
5048 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
5049 				    SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,  in gfx_v11_0_ring_emit_gds_switch()
5053 	gfx_v11_0_write_data_to_reg(ring, 0, false,  in gfx_v11_0_ring_emit_gds_switch()
5054 				    SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,  in gfx_v11_0_ring_emit_gds_switch()
5086 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v11_0_late_init()
5090 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v11_0_late_init()
5094 	r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);  in gfx_v11_0_late_init()
5097 	return 0;  in gfx_v11_0_late_init()
5105 	rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);  in gfx_v11_0_is_rlc_enabled()
5117 	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);  in gfx_v11_0_set_safe_mode()
5120 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_set_safe_mode()
5121 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),  in gfx_v11_0_set_safe_mode()
5130 	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);  in gfx_v11_0_unset_safe_mode()
5141 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_perf_clk()
5149 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_perf_clk()
5160 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_sram_fgcg()
5168 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_sram_fgcg()
5179 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_repeater_fgcg()
5187 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_repeater_fgcg()
5202 			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_medium_grain_clock_gating()
5209 				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_medium_grain_clock_gating()
5213 			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_medium_grain_clock_gating()
5220 				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_medium_grain_clock_gating()
5238 		def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_update_coarse_grain_clock_gating()
5251 			WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5253 		/* enable cgcg FSM(0x0000363F) */  in gfx_v11_0_update_coarse_grain_clock_gating()
5254 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5258 			data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
5264 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
5269 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5272 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);  in gfx_v11_0_update_coarse_grain_clock_gating()
5276 			data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
5282 			data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
5287 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5289 		/* set IDLE_POLL_COUNT(0x00900100) */  in gfx_v11_0_update_coarse_grain_clock_gating()
5290 		def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5293 		data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |  in gfx_v11_0_update_coarse_grain_clock_gating()
5294 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);  in gfx_v11_0_update_coarse_grain_clock_gating()
5297 			WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5299 		data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5304 		WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5306 		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5308 		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5312 			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5314 			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5318 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5327 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5330 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);  in gfx_v11_0_update_coarse_grain_clock_gating()
5338 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5340 		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5342 		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5346 			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);  in gfx_v11_0_update_coarse_grain_clock_gating()
5348 			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);  in gfx_v11_0_update_coarse_grain_clock_gating()
5356 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v11_0_update_gfx_clock_gating()
5376 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v11_0_update_gfx_clock_gating()
5378 	return 0;  in gfx_v11_0_update_gfx_clock_gating()
5386 	reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);  in gfx_v11_0_update_spm_vmid()
5397 			WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);  in gfx_v11_0_update_spm_vmid()
5399 			WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);  in gfx_v11_0_update_spm_vmid()
5428 	u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);  in gfx_v11_cntl_power_gating()
5435 	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);  in gfx_v11_cntl_power_gating()
5439 		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_cntl_power_gating()
5440 		case IP_VERSION(11, 0, 1):  in gfx_v11_cntl_power_gating()
5441 		case IP_VERSION(11, 0, 4):  in gfx_v11_cntl_power_gating()
5442 		case IP_VERSION(11, 5, 0):  in gfx_v11_cntl_power_gating()
5446 			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);  in gfx_v11_cntl_power_gating()
5456 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v11_cntl_pg()
5460 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v11_cntl_pg()
5470 		return 0;  in gfx_v11_0_set_powergating_state()
5472 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_set_powergating_state()
5473 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_set_powergating_state()
5474 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_set_powergating_state()
5475 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_set_powergating_state()
5478 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_set_powergating_state()
5479 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_set_powergating_state()
5480 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_set_powergating_state()
5497 	return 0;  in gfx_v11_0_set_powergating_state()
5506 	        return 0;  in gfx_v11_0_set_clockgating_state()
5508 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {  in gfx_v11_0_set_clockgating_state()
5509 	case IP_VERSION(11, 0, 0):  in gfx_v11_0_set_clockgating_state()
5510 	case IP_VERSION(11, 0, 1):  in gfx_v11_0_set_clockgating_state()
5511 	case IP_VERSION(11, 0, 2):  in gfx_v11_0_set_clockgating_state()
5512 	case IP_VERSION(11, 0, 3):  in gfx_v11_0_set_clockgating_state()
5513 	case IP_VERSION(11, 0, 4):  in gfx_v11_0_set_clockgating_state()
5514 	case IP_VERSION(11, 5, 0):  in gfx_v11_0_set_clockgating_state()
5525 	return 0;  in gfx_v11_0_set_clockgating_state()
5534 	data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);  in gfx_v11_0_get_clockgating_state()
5551 	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);  in gfx_v11_0_get_clockgating_state()
5560 	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);  in gfx_v11_0_get_clockgating_state()
5584 		wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);  in gfx_v11_0_ring_get_wptr_gfx()
5585 		wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;  in gfx_v11_0_ring_get_wptr_gfx()
5601 		WREG32_SOC15(GC, 0, regCP_RB0_WPTR,  in gfx_v11_0_ring_set_wptr_gfx()
5603 		WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,  in gfx_v11_0_ring_set_wptr_gfx()
5657 		reg_mem_engine = 0;  in gfx_v11_0_ring_emit_hdp_flush()
5663 	gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,  in gfx_v11_0_ring_emit_hdp_flush()
5666 			       ref_and_mask, ref_and_mask, 0x20);  in gfx_v11_0_ring_emit_hdp_flush()
5675 	u32 header, control = 0;  in gfx_v11_0_ring_emit_ib_gfx()
5696 		control |= 0x400000;  in gfx_v11_0_ring_emit_ib_gfx()
5699 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */  in gfx_v11_0_ring_emit_ib_gfx()
5702 		(2 << 0) |  in gfx_v11_0_ring_emit_ib_gfx()
5719 		control |= 0x40000000;  in gfx_v11_0_ring_emit_ib_compute()
5729 	 * GDS to 0 for this ring (me/pipe).  in gfx_v11_0_ring_emit_ib_compute()
5738 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */  in gfx_v11_0_ring_emit_ib_compute()
5741 				(2 << 0) |  in gfx_v11_0_ring_emit_ib_compute()
5764 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));  in gfx_v11_0_ring_emit_fence()
5771 		BUG_ON(addr & 0x7);  in gfx_v11_0_ring_emit_fence()
5773 		BUG_ON(addr & 0x3);  in gfx_v11_0_ring_emit_fence()
5779 			 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);  in gfx_v11_0_ring_emit_fence()
5788 	gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),  in gfx_v11_0_ring_emit_pipeline_sync()
5789 			       upper_32_bits(addr), seq, 0xffffffff, 4);  in gfx_v11_0_ring_emit_pipeline_sync()
5796 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));  in gfx_v11_0_ring_invalidate_tlbs()
5808 		gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);  in gfx_v11_0_ring_emit_vm_flush()
5815 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v11_0_ring_emit_vm_flush()
5816 		amdgpu_ring_write(ring, 0x0);  in gfx_v11_0_ring_emit_vm_flush()
5822 	ring->set_q_mode_offs = 0;  in gfx_v11_0_ring_emit_vm_flush()
5836 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v11_0_ring_emit_fence_kiq()
5845 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v11_0_ring_emit_fence_kiq()
5846 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));  in gfx_v11_0_ring_emit_fence_kiq()
5847 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));  in gfx_v11_0_ring_emit_fence_kiq()
5848 		amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_fence_kiq()
5849 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */  in gfx_v11_0_ring_emit_fence_kiq()
5856 	uint32_t dw2 = 0;  in gfx_v11_0_ring_emit_cntxcntl()
5858 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */  in gfx_v11_0_ring_emit_cntxcntl()
5861 		dw2 |= 0x8001;  in gfx_v11_0_ring_emit_cntxcntl()
5863 		dw2 |= 0x01000000;  in gfx_v11_0_ring_emit_cntxcntl()
5865 		dw2 |= 0x10002;  in gfx_v11_0_ring_emit_cntxcntl()
5870 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_cntxcntl()
5881 	/* discard following DWs if *cond_exec_gpu_addr==0 */  in gfx_v11_0_ring_emit_init_cond_exec()
5882 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_init_cond_exec()
5885 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_init_cond_exec()
5921 	amdgpu_ring_write(ring, shadow_va ? 1 : 0);  in gfx_v11_0_ring_emit_gfx_shadow()
5922 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_gfx_shadow()
5945 		amdgpu_ring_write(ring, 0x1);  in gfx_v11_0_ring_emit_gfx_shadow()
5956 			  PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);  in gfx_v11_0_ring_emit_gfx_shadow()
5958 			  PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);  in gfx_v11_0_ring_emit_gfx_shadow()
5971 			*ring->set_q_mode_ptr = 0;  in gfx_v11_0_ring_emit_gfx_shadow()
5983 	int i, r = 0;  in gfx_v11_0_ring_preempt_ib()
5985 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in gfx_v11_0_ring_preempt_ib()
6014 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v11_0_ring_preempt_ib()
6034 	struct v10_de_ib_state de_payload = {0};  in gfx_v11_0_ring_emit_de_meta()
6041 				  gfx[0].gfx_meta_data) +  in gfx_v11_0_ring_emit_de_meta()
6049 				  gfx[0].gds_backup) +  in gfx_v11_0_ring_emit_de_meta()
6070 				 WRITE_DATA_CACHE_POLICY(0));  in gfx_v11_0_ring_emit_de_meta()
6085 	uint32_t v = secure ? FRAME_TMZ : 0;  in gfx_v11_0_ring_emit_frame_cntl()
6087 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));  in gfx_v11_0_ring_emit_frame_cntl()
6088 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));  in gfx_v11_0_ring_emit_frame_cntl()
6097 	amdgpu_ring_write(ring, 0 |	/* src: register*/  in gfx_v11_0_ring_emit_rreg()
6101 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_rreg()
6111 	uint32_t cmd = 0;  in gfx_v11_0_ring_emit_wreg()
6127 	amdgpu_ring_write(ring, 0);  in gfx_v11_0_ring_emit_wreg()
6134 	gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);  in gfx_v11_0_ring_emit_reg_wait()
6143 	gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,  in gfx_v11_0_ring_emit_reg_write_reg_wait()
6144 			       ref, mask, 0x20);  in gfx_v11_0_ring_emit_reg_write_reg_wait()
6151 	uint32_t value = 0;  in gfx_v11_0_ring_soft_recovery()
6153 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);  in gfx_v11_0_ring_soft_recovery()
6154 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);  in gfx_v11_0_ring_soft_recovery()
6157 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v11_0_ring_soft_recovery()
6158 	WREG32_SOC15(GC, 0, regSQ_CMD, value);  in gfx_v11_0_ring_soft_recovery()
6159 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v11_0_ring_soft_recovery()
6171 		case 0:  in gfx_v11_0_set_gfx_eop_interrupt_state()
6172 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);  in gfx_v11_0_set_gfx_eop_interrupt_state()
6175 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);  in gfx_v11_0_set_gfx_eop_interrupt_state()
6190 					    TIME_STAMP_INT_ENABLE, 0);  in gfx_v11_0_set_gfx_eop_interrupt_state()
6192 					    GENERIC0_INT_ENABLE, 0);  in gfx_v11_0_set_gfx_eop_interrupt_state()
6222 		case 0:  in gfx_v11_0_set_compute_eop_interrupt_state()
6223 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
6226 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
6229 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
6232 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);  in gfx_v11_0_set_compute_eop_interrupt_state()
6247 					     TIME_STAMP_INT_ENABLE, 0);  in gfx_v11_0_set_compute_eop_interrupt_state()
6249 					     GENERIC0_INT_ENABLE, 0);  in gfx_v11_0_set_compute_eop_interrupt_state()
6272 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);  in gfx_v11_0_set_eop_interrupt_state()
6275 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);  in gfx_v11_0_set_eop_interrupt_state()
6278 		gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);  in gfx_v11_0_set_eop_interrupt_state()
6292 	return 0;  in gfx_v11_0_set_eop_interrupt_state()
6302 	uint32_t mes_queue_id = entry->src_data[0];  in gfx_v11_0_eop_irq()
6319 		me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v11_0_eop_irq()
6320 		pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v11_0_eop_irq()
6321 		queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v11_0_eop_irq()
6324 		case 0:  in gfx_v11_0_eop_irq()
6325 			if (pipe_id == 0)  in gfx_v11_0_eop_irq()
6326 				amdgpu_fence_process(&adev->gfx.gfx_ring[0]);  in gfx_v11_0_eop_irq()
6332 			for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_eop_irq()
6347 	return 0;  in gfx_v11_0_eop_irq()
6361 		for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_0_set_priv_reg_fault_state()
6362 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {  in gfx_v11_0_set_priv_reg_fault_state()
6369 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_priv_reg_fault_state()
6374 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v11_0_set_priv_reg_fault_state()
6375 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v11_0_set_priv_reg_fault_state()
6383 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_priv_reg_fault_state()
6393 	return 0;  in gfx_v11_0_set_priv_reg_fault_state()
6407 		for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_0_set_bad_op_fault_state()
6408 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {  in gfx_v11_0_set_bad_op_fault_state()
6415 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_bad_op_fault_state()
6420 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v11_0_set_bad_op_fault_state()
6421 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v11_0_set_bad_op_fault_state()
6429 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_bad_op_fault_state()
6438 	return 0;  in gfx_v11_0_set_bad_op_fault_state()
6452 		for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_0_set_priv_inst_fault_state()
6453 			for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {  in gfx_v11_0_set_priv_inst_fault_state()
6460 								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);  in gfx_v11_0_set_priv_inst_fault_state()
6470 	return 0;  in gfx_v11_0_set_priv_inst_fault_state()
6480 	me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v11_0_handle_priv_fault()
6481 	pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v11_0_handle_priv_fault()
6482 	queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v11_0_handle_priv_fault()
6485 	case 0:  in gfx_v11_0_handle_priv_fault()
6486 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v11_0_handle_priv_fault()
6495 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v11_0_handle_priv_fault()
6514 	return 0;  in gfx_v11_0_priv_reg_irq()
6523 	return 0;  in gfx_v11_0_bad_op_irq()
6532 	return 0;  in gfx_v11_0_priv_inst_irq()
6542 	return 0;  in gfx_v11_0_rlc_gc_fed_irq()
6545 #if 0
6552 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6554 	target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6560 			tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6562 					    GENERIC2_INT_ENABLE, 0);
6563 			WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6567 					    GENERIC2_INT_ENABLE, 0);
6570 			tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6573 			WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6585 	return 0;
6603 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */  in gfx_v11_0_emit_mem_sync()
6604 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */  in gfx_v11_0_emit_mem_sync()
6605 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */  in gfx_v11_0_emit_mem_sync()
6606 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */  in gfx_v11_0_emit_mem_sync()
6607 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */  in gfx_v11_0_emit_mem_sync()
6608 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */  in gfx_v11_0_emit_mem_sync()
6642 	int r = 0;  in gfx_v11_0_reset_kcq()
6670 	uint32_t i, j, k, reg, index = 0;  in gfx_v11_ip_print()
6676 	for (i = 0; i < reg_count; i++)  in gfx_v11_ip_print()
6677 		drm_printf(p, "%-50s \t 0x%08x\n",  in gfx_v11_ip_print()
6691 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v11_ip_print()
6692 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v11_ip_print()
6693 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {  in gfx_v11_ip_print()
6695 				for (reg = 0; reg < reg_count; reg++) {  in gfx_v11_ip_print()
6696 					drm_printf(p, "%-50s \t 0x%08x\n",  in gfx_v11_ip_print()
6709 	index = 0;  in gfx_v11_ip_print()
6716 	for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_ip_print()
6717 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {  in gfx_v11_ip_print()
6718 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {  in gfx_v11_ip_print()
6720 				for (reg = 0; reg < reg_count; reg++) {  in gfx_v11_ip_print()
6721 					drm_printf(p, "%-50s \t 0x%08x\n",  in gfx_v11_ip_print()
6734 	uint32_t i, j, k, reg, index = 0;  in gfx_v11_ip_dump()
6741 	for (i = 0; i < reg_count; i++)  in gfx_v11_ip_dump()
6752 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v11_ip_dump()
6753 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v11_ip_dump()
6754 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {  in gfx_v11_ip_dump()
6756 				soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);  in gfx_v11_ip_dump()
6757 				for (reg = 0; reg < reg_count; reg++) {  in gfx_v11_ip_dump()
6766 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_ip_dump()
6774 	index = 0;  in gfx_v11_ip_dump()
6778 	for (i = 0; i < adev->gfx.me.num_me; i++) {  in gfx_v11_ip_dump()
6779 		for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {  in gfx_v11_ip_dump()
6780 			for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {  in gfx_v11_ip_dump()
6781 				soc21_grbm_select(adev, i, j, k, 0);  in gfx_v11_ip_dump()
6783 				for (reg = 0; reg < reg_count; reg++) {  in gfx_v11_ip_dump()
6792 	soc21_grbm_select(adev, 0, 0, 0, 0);  in gfx_v11_ip_dump()
6800 	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));  in gfx_v11_0_ring_emit_cleaner_shader()
6801 	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */  in gfx_v11_0_ring_emit_cleaner_shader()
6842 	.align_mask = 0xff,
6843 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6898 	.align_mask = 0xff,
6899 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6940 	.align_mask = 0xff,
6941 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6971 	adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;  in gfx_v11_0_set_ring_funcs()
6973 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v11_0_set_ring_funcs()
6976 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v11_0_set_ring_funcs()
7018 	adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */  in gfx_v11_0_set_irq_funcs()
7044 	adev->gds.gds_size = 0x1000;  in gfx_v11_0_set_gds_init()
7075 	WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);  in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
7081 	data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);  in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7082 	data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);  in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7099 	cu_active_bitmap = 0;  in gfx_v11_0_get_cu_active_bitmap_per_sh()
7101 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {  in gfx_v11_0_get_cu_active_bitmap_per_sh()
7114 	int i, j, k, counter, active_cu_number = 0;  in gfx_v11_0_get_cu_info()
7124 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v11_0_get_cu_info()
7125 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v11_0_get_cu_info()
7130 			counter = 0;  in gfx_v11_0_get_cu_info()
7131 			gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v11_0_get_cu_info()
7143 			 *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}  in gfx_v11_0_get_cu_info()
7144 			 *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}  in gfx_v11_0_get_cu_info()
7145 			 *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}  in gfx_v11_0_get_cu_info()
7146 			 *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}  in gfx_v11_0_get_cu_info()
7147 			 *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}  in gfx_v11_0_get_cu_info()
7152 			cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;  in gfx_v11_0_get_cu_info()
7154 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {  in gfx_v11_0_get_cu_info()
7163 	gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v11_0_get_cu_info()
7169 	return 0;  in gfx_v11_0_get_cu_info()
7176 	.minor = 0,
7177 	.rev = 0,