Lines Matching +full:needs +full:- +full:hpd
94 (0x13830 - 0x7030) >> 2,
101 uint32_t hpd; member
107 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
127 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
132 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
154 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
158 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
163 if (crtc >= adev->mode_info.num_crtc) in dce_v6_0_vblank_get_counter()
174 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_init()
175 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_init()
183 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_fini()
184 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_fini()
188 * dce_v6_0_page_flip - pageflip callback.
204 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
205 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v6_0_page_flip()
208 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
211 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
212 fb->pitches[0] / fb->format->cpp[0]); in dce_v6_0_page_flip()
214 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
217 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
220 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
226 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v6_0_crtc_get_scanoutpos()
227 return -EINVAL; in dce_v6_0_crtc_get_scanoutpos()
236 * dce_v6_0_hpd_sense - hpd sense callback.
239 * @hpd: hpd (hotplug detect) pin
245 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_sense() argument
249 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_sense()
252 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & in dce_v6_0_hpd_sense()
260 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
263 * @hpd: hpd (hotplug detect) pin
265 * Set the polarity of the hpd pin (evergreen+).
268 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_set_polarity() argument
271 bool connected = dce_v6_0_hpd_sense(adev, hpd); in dce_v6_0_hpd_set_polarity()
273 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_set_polarity()
276 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_set_polarity()
281 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_set_polarity()
285 int hpd) in dce_v6_0_hpd_int_ack() argument
289 if (hpd >= adev->mode_info.num_hpd) { in dce_v6_0_hpd_int_ack()
290 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v6_0_hpd_int_ack()
294 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_int_ack()
296 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_int_ack()
300 * dce_v6_0_hpd_init - hpd setup callback.
304 * Setup the hpd pins used by the card (evergreen+).
305 * Enable the pin, set the polarity, and enable the hpd interrupts.
318 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_init()
321 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
323 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
325 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v6_0_hpd_init()
326 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v6_0_hpd_init()
327 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v6_0_hpd_init()
332 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
334 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
338 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
339 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
340 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
346 * dce_v6_0_hpd_fini - hpd tear down callback.
350 * Tear down the hpd pins used by the card (evergreen+).
351 * Disable the hpd interrupts.
364 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_fini()
367 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_fini()
369 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_fini()
371 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_fini()
387 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_is_display_hung()
395 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_is_display_hung()
420 switch (adev->asic_type) { in dce_v6_0_get_num_crtc()
458 struct drm_device *dev = encoder->dev; in dce_v6_0_program_fmt()
462 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_program_fmt()
470 dither = amdgpu_connector->dither; in dce_v6_0_program_fmt()
474 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v6_0_program_fmt()
509 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
513 * si_get_number_of_dram_channels - get the number of dram channels
565 * dce_v6_0_dram_bandwidth - get the dram bandwidth
581 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()
583 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()
594 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
610 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()
612 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()
623 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
639 sclk.full = dfixed_const(wm->sclk); in dce_v6_0_data_return_bandwidth()
652 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
668 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v6_0_dmif_request_bandwidth()
683 * dce_v6_0_available_bandwidth - get the min available bandwidth
702 * dce_v6_0_average_bandwidth - get the average available bandwidth
723 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v6_0_average_bandwidth()
725 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v6_0_average_bandwidth()
726 src_width.full = dfixed_const(wm->src_width); in dce_v6_0_average_bandwidth()
728 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v6_0_average_bandwidth()
735 * dce_v6_0_latency_watermark - get the latency watermark
750 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v6_0_latency_watermark()
751 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
752 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
758 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
763 if ((wm->vsc.full > a.full) || in dce_v6_0_latency_watermark()
764 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
765 (wm->vtaps >= 5) || in dce_v6_0_latency_watermark()
766 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v6_0_latency_watermark()
772 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
774 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v6_0_latency_watermark()
777 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v6_0_latency_watermark()
779 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v6_0_latency_watermark()
786 if (line_fill_time < wm->active_time) in dce_v6_0_latency_watermark()
789 return latency + (line_fill_time - wm->active_time); in dce_v6_0_latency_watermark()
794 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
807 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
814 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
827 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
834 * dce_v6_0_check_latency_hiding - check latency hiding
844 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
845 u32 line_time = wm->active_time + wm->blank_time; in dce_v6_0_check_latency_hiding()
851 if (wm->vsc.full > a.full) in dce_v6_0_check_latency_hiding()
854 if (lb_partitions <= (wm->vtaps + 1)) in dce_v6_0_check_latency_hiding()
860 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v6_0_check_latency_hiding()
869 * dce_v6_0_program_watermarks - program display watermarks
883 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v6_0_program_watermarks()
895 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
896 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v6_0_program_watermarks()
897 (u32)mode->clock); in dce_v6_0_program_watermarks()
898 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v6_0_program_watermarks()
899 (u32)mode->clock); in dce_v6_0_program_watermarks()
907 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
913 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
914 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
917 wm_high.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
918 wm_high.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
920 wm_high.blank_time = line_time - wm_high.active_time; in dce_v6_0_program_watermarks()
922 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
924 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
926 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
934 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
940 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
941 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
944 wm_low.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
945 wm_low.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
947 wm_low.blank_time = line_time - wm_low.active_time; in dce_v6_0_program_watermarks()
949 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
951 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
953 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
970 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
978 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
985 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
989 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
997 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
1001 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
1008 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v6_0_program_watermarks()
1012 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
1016 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
1017 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
1021 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
1024 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
1025 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
1029 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
1032 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
1033 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
1036 amdgpu_crtc->line_time = line_time; in dce_v6_0_program_watermarks()
1037 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v6_0_program_watermarks()
1040 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v6_0_program_watermarks()
1045 * dce_v6_0_line_buffer_adjust - Set up the line buffer
1064 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust()
1071 * 0 - half lb in dce_v6_0_line_buffer_adjust()
1072 * 2 - whole lb, other crtc must be disabled in dce_v6_0_line_buffer_adjust()
1076 * non-linked crtcs for maximum line buffer allocation. in dce_v6_0_line_buffer_adjust()
1078 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1091 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1096 for (i = 0; i < adev->usec_timeout; i++) { in dce_v6_0_line_buffer_adjust()
1103 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1119 * dce_v6_0_bandwidth_update - program display watermarks
1133 if (!adev->mode_info.mode_config_initialized) in dce_v6_0_bandwidth_update()
1138 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_bandwidth_update()
1139 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1142 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { in dce_v6_0_bandwidth_update()
1143 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1144 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1145 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1146 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1147 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1148 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1157 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_connected_pins()
1158 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, in dce_v6_0_audio_get_connected_pins()
1162 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_get_connected_pins()
1164 adev->mode_info.audio.pin[i].connected = true; in dce_v6_0_audio_get_connected_pins()
1175 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_pin()
1176 if (adev->mode_info.audio.pin[i].connected) in dce_v6_0_audio_get_pin()
1177 return &adev->mode_info.audio.pin[i]; in dce_v6_0_audio_get_pin()
1185 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_audio_select_pin()
1187 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_select_pin()
1189 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v6_0_audio_select_pin()
1192 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, in dce_v6_0_audio_select_pin()
1194 dig->afmt->pin->id)); in dce_v6_0_audio_select_pin()
1200 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_latency_fields()
1203 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_latency_fields()
1212 if (connector->encoder == encoder) { in dce_v6_0_audio_write_latency_fields()
1224 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_audio_write_latency_fields()
1227 if (connector->latency_present[interlace]) { in dce_v6_0_audio_write_latency_fields()
1229 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1231 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1238 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_latency_fields()
1244 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_speaker_allocation()
1247 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_speaker_allocation()
1257 if (connector->encoder == encoder) { in dce_v6_0_audio_write_speaker_allocation()
1269 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); in dce_v6_0_audio_write_speaker_allocation()
1276 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1283 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) in dce_v6_0_audio_write_speaker_allocation()
1297 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1305 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_sad_regs()
1308 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_sad_regs()
1332 if (connector->encoder == encoder) { in dce_v6_0_audio_write_sad_regs()
1344 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); in dce_v6_0_audio_write_sad_regs()
1353 int max_channels = -1; in dce_v6_0_audio_write_sad_regs()
1359 if (sad->format == eld_reg_to_type[i][1]) { in dce_v6_0_audio_write_sad_regs()
1360 if (sad->channels > max_channels) { in dce_v6_0_audio_write_sad_regs()
1362 MAX_CHANNELS, sad->channels); in dce_v6_0_audio_write_sad_regs()
1364 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v6_0_audio_write_sad_regs()
1366 SUPPORTED_FREQUENCIES, sad->freq); in dce_v6_0_audio_write_sad_regs()
1367 max_channels = sad->channels; in dce_v6_0_audio_write_sad_regs()
1370 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v6_0_audio_write_sad_regs()
1371 stereo_freqs |= sad->freq; in dce_v6_0_audio_write_sad_regs()
1379 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v6_0_audio_write_sad_regs()
1393 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v6_0_audio_enable()
1415 adev->mode_info.audio.enabled = true; in dce_v6_0_audio_init()
1417 switch (adev->asic_type) { in dce_v6_0_audio_init()
1422 adev->mode_info.audio.num_pins = 6; in dce_v6_0_audio_init()
1425 adev->mode_info.audio.num_pins = 2; in dce_v6_0_audio_init()
1429 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_init()
1430 adev->mode_info.audio.pin[i].channels = -1; in dce_v6_0_audio_init()
1431 adev->mode_info.audio.pin[i].rate = -1; in dce_v6_0_audio_init()
1432 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v6_0_audio_init()
1433 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v6_0_audio_init()
1434 adev->mode_info.audio.pin[i].category_code = 0; in dce_v6_0_audio_init()
1435 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_init()
1436 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v6_0_audio_init()
1437 adev->mode_info.audio.pin[i].id = i; in dce_v6_0_audio_init()
1440 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_init()
1453 if (!adev->mode_info.audio.enabled) in dce_v6_0_audio_fini()
1456 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v6_0_audio_fini()
1457 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_fini()
1459 adev->mode_info.audio.enabled = false; in dce_v6_0_audio_fini()
1464 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_vbi_packet()
1467 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_vbi_packet()
1470 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_vbi_packet()
1474 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_vbi_packet()
1480 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_acr()
1484 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_acr()
1487 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1491 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1493 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1495 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1496 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1498 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1500 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1502 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1503 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1505 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1507 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1509 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1510 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1512 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1518 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_avi_infoframe()
1521 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_avi_infoframe()
1542 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1544 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1546 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1548 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1551 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_set_avi_infoframe()
1555 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_avi_infoframe()
1560 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_dto()
1562 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_audio_set_dto()
1574 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); in dce_v6_0_audio_set_dto()
1594 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_packet()
1597 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_packet()
1600 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1602 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1604 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1606 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1608 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1610 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1612 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1619 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1621 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1623 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1625 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1628 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1630 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1633 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1638 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_mute()
1641 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_mute()
1644 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); in dce_v6_0_audio_set_mute()
1646 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); in dce_v6_0_audio_set_mute()
1651 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_hdmi_enable()
1654 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_hdmi_enable()
1658 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1663 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1665 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1667 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1669 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1671 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1673 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1678 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1680 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1682 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1688 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_dp_enable()
1691 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_dp_enable()
1695 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1697 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1699 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1701 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1703 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1708 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1710 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); in dce_v6_0_audio_dp_enable()
1717 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_setmode()
1720 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_setmode()
1727 if (!dig || !dig->afmt) in dce_v6_0_afmt_setmode()
1732 if (connector->encoder == encoder) { in dce_v6_0_afmt_setmode()
1744 if (!dig->afmt->enabled) in dce_v6_0_afmt_setmode()
1747 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); in dce_v6_0_afmt_setmode()
1748 if (!dig->afmt->pin) in dce_v6_0_afmt_setmode()
1751 if (encoder->crtc) { in dce_v6_0_afmt_setmode()
1752 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_afmt_setmode()
1753 bpc = amdgpu_crtc->bpc; in dce_v6_0_afmt_setmode()
1757 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_setmode()
1764 dce_v6_0_audio_set_dto(encoder, mode->clock); in dce_v6_0_afmt_setmode()
1766 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); in dce_v6_0_afmt_setmode()
1768 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); in dce_v6_0_afmt_setmode()
1781 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); in dce_v6_0_afmt_setmode()
1786 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_enable()
1789 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_enable()
1791 if (!dig || !dig->afmt) in dce_v6_0_afmt_enable()
1795 if (enable && dig->afmt->enabled) in dce_v6_0_afmt_enable()
1798 if (!enable && !dig->afmt->enabled) in dce_v6_0_afmt_enable()
1801 if (!enable && dig->afmt->pin) { in dce_v6_0_afmt_enable()
1802 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_enable()
1803 dig->afmt->pin = NULL; in dce_v6_0_afmt_enable()
1806 dig->afmt->enabled = enable; in dce_v6_0_afmt_enable()
1809 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v6_0_afmt_enable()
1816 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v6_0_afmt_init()
1817 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_init()
1820 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_init()
1821 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v6_0_afmt_init()
1822 if (adev->mode_info.afmt[i]) { in dce_v6_0_afmt_init()
1823 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v6_0_afmt_init()
1824 adev->mode_info.afmt[i]->id = i; in dce_v6_0_afmt_init()
1827 kfree(adev->mode_info.afmt[j]); in dce_v6_0_afmt_init()
1828 adev->mode_info.afmt[j] = NULL; in dce_v6_0_afmt_init()
1831 return -ENOMEM; in dce_v6_0_afmt_init()
1841 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_fini()
1842 kfree(adev->mode_info.afmt[i]); in dce_v6_0_afmt_fini()
1843 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_fini()
1860 struct drm_device *dev = crtc->dev; in dce_v6_0_vga_enable()
1864 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v6_0_vga_enable()
1865 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); in dce_v6_0_vga_enable()
1871 struct drm_device *dev = crtc->dev; in dce_v6_0_grph_enable()
1874 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
1882 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_do_set_base()
1895 if (!atomic && !crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
1903 target_fb = crtc->primary->fb; in dce_v6_0_crtc_do_set_base()
1908 obj = target_fb->obj[0]; in dce_v6_0_crtc_do_set_base()
1915 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v6_0_crtc_do_set_base()
1919 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1927 switch (target_fb->format->format) { in dce_v6_0_crtc_do_set_base()
1978 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1988 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
2003 &target_fb->format->format); in dce_v6_0_crtc_do_set_base()
2004 return -EINVAL; in dce_v6_0_crtc_do_set_base()
2034 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2036 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2038 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2040 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2042 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2044 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
2045 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
2052 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2059 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2060 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2061 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2062 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2063 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
2064 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
2066 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v6_0_crtc_do_set_base()
2067 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2071 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2072 target_fb->height); in dce_v6_0_crtc_do_set_base()
2075 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2077 viewport_w = crtc->mode.hdisplay; in dce_v6_0_crtc_do_set_base()
2078 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v6_0_crtc_do_set_base()
2080 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2084 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2086 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
2087 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v6_0_crtc_do_set_base()
2105 struct drm_device *dev = crtc->dev; in dce_v6_0_set_interleave()
2109 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_set_interleave()
2110 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2113 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2120 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_load_lut()
2125 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v6_0_crtc_load_lut()
2127 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2130 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2132 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2134 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2138 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2140 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2141 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2142 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2144 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2146 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2148 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2149 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2151 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2152 r = crtc->gamma_store; in dce_v6_0_crtc_load_lut()
2153 g = r + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2154 b = g + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2156 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2162 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2167 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2170 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2173 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2177 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2185 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_pick_dig_encoder()
2187 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_pick_dig_encoder()
2189 return dig->linkb ? 1 : 0; in dce_v6_0_pick_dig_encoder()
2191 return dig->linkb ? 3 : 2; in dce_v6_0_pick_dig_encoder()
2193 return dig->linkb ? 5 : 4; in dce_v6_0_pick_dig_encoder()
2197 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v6_0_pick_dig_encoder()
2203 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2208 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2220 struct drm_device *dev = crtc->dev; in dce_v6_0_pick_pll()
2225 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v6_0_pick_pll()
2226 if (adev->clock.dp_extclk) in dce_v6_0_pick_pll()
2250 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_lock_cursor()
2254 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2259 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2265 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_hide_cursor()
2267 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2277 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_show_cursor()
2279 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2280 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2281 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2282 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2284 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2295 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_cursor_move_locked()
2298 int w = amdgpu_crtc->cursor_width; in dce_v6_0_cursor_move_locked()
2300 amdgpu_crtc->cursor_x = x; in dce_v6_0_cursor_move_locked()
2301 amdgpu_crtc->cursor_y = y; in dce_v6_0_cursor_move_locked()
2304 x += crtc->x; in dce_v6_0_cursor_move_locked()
2305 y += crtc->y; in dce_v6_0_cursor_move_locked()
2306 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v6_0_cursor_move_locked()
2309 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v6_0_cursor_move_locked()
2313 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v6_0_cursor_move_locked()
2317 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2318 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2319 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2320 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v6_0_cursor_move_locked()
2357 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v6_0_crtc_cursor_set2()
2358 (height > amdgpu_crtc->max_cursor_height)) { in dce_v6_0_crtc_cursor_set2()
2360 return -EINVAL; in dce_v6_0_crtc_cursor_set2()
2365 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v6_0_crtc_cursor_set2()
2366 return -ENOENT; in dce_v6_0_crtc_cursor_set2()
2376 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; in dce_v6_0_crtc_cursor_set2()
2384 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v6_0_crtc_cursor_set2()
2388 if (width != amdgpu_crtc->cursor_width || in dce_v6_0_crtc_cursor_set2()
2389 height != amdgpu_crtc->cursor_height || in dce_v6_0_crtc_cursor_set2()
2390 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v6_0_crtc_cursor_set2()
2391 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v6_0_crtc_cursor_set2()
2394 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v6_0_crtc_cursor_set2()
2395 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v6_0_crtc_cursor_set2()
2399 amdgpu_crtc->cursor_width = width; in dce_v6_0_crtc_cursor_set2()
2400 amdgpu_crtc->cursor_height = height; in dce_v6_0_crtc_cursor_set2()
2401 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v6_0_crtc_cursor_set2()
2402 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v6_0_crtc_cursor_set2()
2409 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_crtc_cursor_set2()
2410 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2416 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2419 amdgpu_crtc->cursor_bo = obj; in dce_v6_0_crtc_cursor_set2()
2427 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_cursor_reset()
2430 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v6_0_cursor_reset()
2431 amdgpu_crtc->cursor_y); in dce_v6_0_cursor_reset()
2470 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_dpms()
2477 amdgpu_crtc->enabled = true; in dce_v6_0_crtc_dpms()
2482 amdgpu_crtc->crtc_id); in dce_v6_0_crtc_dpms()
2483 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v6_0_crtc_dpms()
2484 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v6_0_crtc_dpms()
2492 if (amdgpu_crtc->enabled) in dce_v6_0_crtc_dpms()
2495 amdgpu_crtc->enabled = false; in dce_v6_0_crtc_dpms()
2520 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_disable()
2526 if (crtc->primary->fb) { in dce_v6_0_crtc_disable()
2530 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v6_0_crtc_disable()
2544 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_crtc_disable()
2545 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2546 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
2547 i != amdgpu_crtc->crtc_id && in dce_v6_0_crtc_disable()
2548 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2556 switch (amdgpu_crtc->pll_id) { in dce_v6_0_crtc_disable()
2560 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v6_0_crtc_disable()
2567 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_disable()
2568 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_disable()
2569 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_disable()
2570 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_disable()
2580 if (!amdgpu_crtc->adjusted_clock) in dce_v6_0_crtc_mode_set()
2581 return -EINVAL; in dce_v6_0_crtc_mode_set()
2590 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
2601 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_mode_fixup()
2605 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_crtc_mode_fixup()
2606 if (encoder->crtc == crtc) { in dce_v6_0_crtc_mode_fixup()
2607 amdgpu_crtc->encoder = encoder; in dce_v6_0_crtc_mode_fixup()
2608 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v6_0_crtc_mode_fixup()
2612 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v6_0_crtc_mode_fixup()
2613 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_mode_fixup()
2614 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_mode_fixup()
2622 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); in dce_v6_0_crtc_mode_fixup()
2623 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
2624 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v6_0_crtc_mode_fixup()
2625 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v6_0_crtc_mode_fixup()
2663 if (!plane->fb) in dce_v6_0_panic_flush()
2666 fb = plane->fb; in dce_v6_0_panic_flush()
2667 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); in dce_v6_0_panic_flush()
2668 adev = drm_to_adev(fb->dev); in dce_v6_0_panic_flush()
2671 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v6_0_panic_flush()
2673 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_panic_flush()
2689 return -ENOMEM; in dce_v6_0_crtc_init()
2691 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); in dce_v6_0_crtc_init()
2693 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v6_0_crtc_init()
2694 amdgpu_crtc->crtc_id = index; in dce_v6_0_crtc_init()
2695 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
2697 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; in dce_v6_0_crtc_init()
2698 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; in dce_v6_0_crtc_init()
2699 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v6_0_crtc_init()
2700 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v6_0_crtc_init()
2702 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
2704 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_init()
2705 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_init()
2706 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_init()
2707 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_init()
2708 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); in dce_v6_0_crtc_init()
2709 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); in dce_v6_0_crtc_init()
2716 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_early_init()
2718 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; in dce_v6_0_early_init()
2719 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; in dce_v6_0_early_init()
2723 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); in dce_v6_0_early_init()
2725 switch (adev->asic_type) { in dce_v6_0_early_init()
2729 adev->mode_info.num_hpd = 6; in dce_v6_0_early_init()
2730 adev->mode_info.num_dig = 6; in dce_v6_0_early_init()
2733 adev->mode_info.num_hpd = 2; in dce_v6_0_early_init()
2734 adev->mode_info.num_dig = 2; in dce_v6_0_early_init()
2737 return -EINVAL; in dce_v6_0_early_init()
2749 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_sw_init()
2751 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2752 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v6_0_sw_init()
2758 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v6_0_sw_init()
2763 /* HPD hotplug */ in dce_v6_0_sw_init()
2764 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); in dce_v6_0_sw_init()
2768 adev->mode_info.mode_config_initialized = true; in dce_v6_0_sw_init()
2770 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v6_0_sw_init()
2771 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v6_0_sw_init()
2772 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2773 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2774 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v6_0_sw_init()
2775 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v6_0_sw_init()
2776 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; in dce_v6_0_sw_init()
2782 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2783 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2786 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2796 return -EINVAL; in dce_v6_0_sw_init()
2807 /* Disable vblank IRQs aggressively for power-saving */ in dce_v6_0_sw_init()
2809 adev_to_drm(adev)->vblank_disable_immediate = true; in dce_v6_0_sw_init()
2811 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); in dce_v6_0_sw_init()
2815 /* Pre-DCE11 */ in dce_v6_0_sw_init()
2816 INIT_DELAYED_WORK(&adev->hotplug_work, in dce_v6_0_sw_init()
2826 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_sw_fini()
2828 drm_edid_free(adev->mode_info.bios_hardcoded_edid); in dce_v6_0_sw_fini()
2836 adev->mode_info.mode_config_initialized = false; in dce_v6_0_sw_fini()
2844 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_hw_init()
2850 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v6_0_hw_init()
2852 /* initialize hpd */ in dce_v6_0_hw_init()
2855 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_init()
2856 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_init()
2867 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_hw_fini()
2871 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_fini()
2872 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_fini()
2877 flush_delayed_work(&adev->hotplug_work); in dce_v6_0_hw_fini()
2884 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_suspend()
2890 adev->mode_info.bl_level = in dce_v6_0_suspend()
2898 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_resume()
2902 adev->mode_info.bl_level); in dce_v6_0_resume()
2907 if (adev->mode_info.bl_encoder) { in dce_v6_0_resume()
2909 adev->mode_info.bl_encoder); in dce_v6_0_resume()
2910 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v6_0_resume()
2927 struct amdgpu_device *adev = ip_block->adev; in dce_v6_0_soft_reset()
2935 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v6_0_soft_reset()
2957 if (crtc >= adev->mode_info.num_crtc) { in dce_v6_0_set_crtc_vblank_interrupt_state()
3016 if (type >= adev->mode_info.num_hpd) { in dce_v6_0_set_hpd_interrupt_state()
3091 unsigned crtc = entry->src_id - 1; in dce_v6_0_crtc_irq()
3096 switch (entry->src_data[0]) { in dce_v6_0_crtc_irq()
3117 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_crtc_irq()
3131 if (type >= adev->mode_info.num_crtc) { in dce_v6_0_set_pageflip_interrupt_state()
3133 return -EINVAL; in dce_v6_0_set_pageflip_interrupt_state()
3156 crtc_id = (entry->src_id - 8) >> 1; in dce_v6_0_pageflip_irq()
3157 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_pageflip_irq()
3159 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v6_0_pageflip_irq()
3161 return -EINVAL; in dce_v6_0_pageflip_irq()
3173 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3174 works = amdgpu_crtc->pflip_works; in dce_v6_0_pageflip_irq()
3175 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v6_0_pageflip_irq()
3176 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v6_0_pageflip_irq()
3178 amdgpu_crtc->pflip_status, in dce_v6_0_pageflip_irq()
3180 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3185 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v6_0_pageflip_irq()
3186 amdgpu_crtc->pflip_works = NULL; in dce_v6_0_pageflip_irq()
3189 if (works->event) in dce_v6_0_pageflip_irq()
3190 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v6_0_pageflip_irq()
3192 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3194 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v6_0_pageflip_irq()
3195 schedule_work(&works->unpin_work); in dce_v6_0_pageflip_irq()
3205 unsigned hpd; in dce_v6_0_hpd_irq() local
3207 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v6_0_hpd_irq()
3208 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_hpd_irq()
3212 hpd = entry->src_data[0]; in dce_v6_0_hpd_irq()
3213 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3214 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
3217 dce_v6_0_hpd_int_ack(adev, hpd); in dce_v6_0_hpd_irq()
3218 schedule_delayed_work(&adev->hotplug_work, 0); in dce_v6_0_hpd_irq()
3219 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v6_0_hpd_irq()
3261 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v6_0_encoder_mode_set()
3267 dce_v6_0_set_interleave(encoder->crtc, mode); in dce_v6_0_encoder_mode_set()
3278 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_encoder_prepare()
3282 if ((amdgpu_encoder->active_device & in dce_v6_0_encoder_prepare()
3286 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_prepare()
3288 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); in dce_v6_0_encoder_prepare()
3289 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v6_0_encoder_prepare()
3290 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v6_0_encoder_prepare()
3300 if (amdgpu_connector->router.cd_valid) in dce_v6_0_encoder_prepare()
3304 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v6_0_encoder_prepare()
3318 struct drm_device *dev = encoder->dev; in dce_v6_0_encoder_commit()
3338 dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_disable()
3339 dig->dig_encoder = -1; in dce_v6_0_encoder_disable()
3341 amdgpu_encoder->active_device = 0; in dce_v6_0_encoder_disable()
3411 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_destroy()
3413 kfree(amdgpu_encoder->enc_priv); in dce_v6_0_encoder_destroy()
3432 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_encoder_add()
3434 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v6_0_encoder_add()
3435 amdgpu_encoder->devices |= supported_device; in dce_v6_0_encoder_add()
3445 encoder = &amdgpu_encoder->base; in dce_v6_0_encoder_add()
3446 switch (adev->mode_info.num_crtc) { in dce_v6_0_encoder_add()
3448 encoder->possible_crtcs = 0x1; in dce_v6_0_encoder_add()
3452 encoder->possible_crtcs = 0x3; in dce_v6_0_encoder_add()
3455 encoder->possible_crtcs = 0xf; in dce_v6_0_encoder_add()
3458 encoder->possible_crtcs = 0x3f; in dce_v6_0_encoder_add()
3462 amdgpu_encoder->enc_priv = NULL; in dce_v6_0_encoder_add()
3463 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v6_0_encoder_add()
3464 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v6_0_encoder_add()
3465 amdgpu_encoder->devices = supported_device; in dce_v6_0_encoder_add()
3466 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v6_0_encoder_add()
3467 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v6_0_encoder_add()
3468 amdgpu_encoder->is_ext_encoder = false; in dce_v6_0_encoder_add()
3469 amdgpu_encoder->caps = caps; in dce_v6_0_encoder_add()
3471 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_encoder_add()
3483 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v6_0_encoder_add()
3484 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v6_0_encoder_add()
3487 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3488 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v6_0_encoder_add()
3491 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3495 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3509 amdgpu_encoder->is_ext_encoder = true; in dce_v6_0_encoder_add()
3510 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_add()
3513 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v6_0_encoder_add()
3540 adev->mode_info.funcs = &dce_v6_0_display_funcs; in dce_v6_0_set_display_funcs()
3560 if (adev->mode_info.num_crtc > 0) in dce_v6_0_set_irq_funcs()
3561 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3563 adev->crtc_irq.num_types = 0; in dce_v6_0_set_irq_funcs()
3564 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; in dce_v6_0_set_irq_funcs()
3566 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3567 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; in dce_v6_0_set_irq_funcs()
3569 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v6_0_set_irq_funcs()
3570 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; in dce_v6_0_set_irq_funcs()