362 struct amdgpu_gfx {  struct
364 	struct amdgpu_gfx_config	config;  argument
365 	struct amdgpu_rlc		rlc;
366 	struct amdgpu_pfp		pfp;
367 	struct amdgpu_ce		ce;
368 	struct amdgpu_me		me;
369 	struct amdgpu_mec		mec;
370 	struct amdgpu_mec_bitmap	mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
371 	struct amdgpu_kiq		kiq[AMDGPU_MAX_GC_INSTANCES];
372 	struct amdgpu_imu		imu;
373 	bool				rs64_enable; /* firmware format */
374 	const struct firmware		*me_fw;	/* ME firmware */
375 	uint32_t			me_fw_version;
376 	const struct firmware		*pfp_fw; /* PFP firmware */
377 	uint32_t			pfp_fw_version;
378 	const struct firmware		*ce_fw;	/* CE firmware */
379 	uint32_t			ce_fw_version;
380 	const struct firmware		*rlc_fw; /* RLC firmware */
381 	uint32_t			rlc_fw_version;
382 	const struct firmware		*mec_fw; /* MEC firmware */
383 	uint32_t			mec_fw_version;
384 	const struct firmware		*mec2_fw; /* MEC2 firmware */
385 	uint32_t			mec2_fw_version;
386 	const struct firmware		*imu_fw; /* IMU firmware */
387 	uint32_t			imu_fw_version;
388 	uint32_t			me_feature_version;
389 	uint32_t			ce_feature_version;
390 	uint32_t			pfp_feature_version;
391 	uint32_t			rlc_feature_version;
392 	uint32_t			rlc_srlc_fw_version;
393 	uint32_t			rlc_srlc_feature_version;
394 	uint32_t			rlc_srlg_fw_version;
395 	uint32_t			rlc_srlg_feature_version;
396 	uint32_t			rlc_srls_fw_version;
397 	uint32_t			rlc_srls_feature_version;
398 	uint32_t			rlcp_ucode_version;
399 	uint32_t			rlcp_ucode_feature_version;
400 	uint32_t			rlcv_ucode_version;
401 	uint32_t			rlcv_ucode_feature_version;
425 	const struct amdgpu_gfx_funcs	*funcs;  argument
447 	struct amdgpu_gfx_ras		*ras;  argument
449 	bool				is_poweron;
451 	struct amdgpu_ring		sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
452 	struct amdgpu_ring_mux          muxer;
454 	bool				cp_gfx_shadow; /* for gfx11 */
456 	uint16_t 			xcc_mask;
457 	uint32_t			num_xcc_per_xcp;
458 	struct mutex			partition_mutex;
459 	bool				mcbp; /* mid command buffer preemption */
462 	uint32_t			*ip_dump_core;
463 	uint32_t			*ip_dump_compute_queues;
464 	uint32_t			*ip_dump_gfx_queues;
489 struct amdgpu_gfx_ras_reg_entry {  argument