Lines Matching full:section
147 struct cper_sec_crashdump_fatal *section; in amdgpu_cper_entry_fill_fatal_section() local
150 section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr + in amdgpu_cper_entry_fill_fatal_section()
157 section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH; in amdgpu_cper_entry_fill_fatal_section()
158 section->body.reg_arr_size = sizeof(reg_data); in amdgpu_cper_entry_fill_fatal_section()
159 section->body.data = reg_data; in amdgpu_cper_entry_fill_fatal_section()
174 struct cper_sec_nonstd_err *section; in amdgpu_cper_entry_fill_runtime_section() local
179 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + in amdgpu_cper_entry_fill_runtime_section()
188 section->hdr.valid_bits.err_info_cnt = 1; in amdgpu_cper_entry_fill_runtime_section()
189 section->hdr.valid_bits.err_context_cnt = 1; in amdgpu_cper_entry_fill_runtime_section()
191 section->info.error_type = RUNTIME; in amdgpu_cper_entry_fill_runtime_section()
192 section->info.ms_chk_bits.err_type_valid = 1; in amdgpu_cper_entry_fill_runtime_section()
193 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; in amdgpu_cper_entry_fill_runtime_section()
194 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); in amdgpu_cper_entry_fill_runtime_section()
196 memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t)); in amdgpu_cper_entry_fill_runtime_section()
208 struct cper_sec_nonstd_err *section; in amdgpu_cper_entry_fill_bad_page_threshold_section() local
211 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + in amdgpu_cper_entry_fill_bad_page_threshold_section()
218 section->hdr.valid_bits.err_info_cnt = 1; in amdgpu_cper_entry_fill_bad_page_threshold_section()
219 section->hdr.valid_bits.err_context_cnt = 1; in amdgpu_cper_entry_fill_bad_page_threshold_section()
221 section->info.error_type = RUNTIME; in amdgpu_cper_entry_fill_bad_page_threshold_section()
222 section->info.ms_chk_bits.err_type_valid = 1; in amdgpu_cper_entry_fill_bad_page_threshold_section()
223 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; in amdgpu_cper_entry_fill_bad_page_threshold_section()
224 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); in amdgpu_cper_entry_fill_bad_page_threshold_section()
227 section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1; in amdgpu_cper_entry_fill_bad_page_threshold_section()
228 section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
229 section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137; in amdgpu_cper_entry_fill_bad_page_threshold_section()
230 section->ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000; in amdgpu_cper_entry_fill_bad_page_threshold_section()
231 section->ctx.reg_dump[CPER_ACA_REG_ADDR_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
232 section->ctx.reg_dump[CPER_ACA_REG_ADDR_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
233 section->ctx.reg_dump[CPER_ACA_REG_MISC0_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
234 section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
235 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2; in amdgpu_cper_entry_fill_bad_page_threshold_section()
236 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff; in amdgpu_cper_entry_fill_bad_page_threshold_section()
237 section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
238 section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x96; in amdgpu_cper_entry_fill_bad_page_threshold_section()
239 section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
240 section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()