amd/amdgpu/amdgpu.h

137 enum amdgpu_ss {
330 enum amdgpu_cp_irq {
345 enum amdgpu_thermal_irq {
352 enum amdgpu_kiq_irq {
361 					   enum amd_ip_block_type block_type,
362 					   enum amd_clockgating_state state);
364 					   enum amd_ip_block_type block_type,
365 					   enum amd_powergating_state state);
369 				   enum amd_ip_block_type block_type);
371 			      enum amd_ip_block_type block_type);
387 	const enum amd_ip_block_type type;
401 				       enum amd_ip_block_type type,
406 			      enum amd_ip_block_type type);
541  * enum amd_reset_method - Methods for resetting AMD GPU devices
565 enum amd_reset_method {
607 	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
647 				 enum amdgpu_reg_state reg_state, void *buf,
701 enum amd_hw_ip_block_type {
758 				      enum amd_hw_ip_block_type block,
761 					enum amd_hw_ip_block_type block,
840 enum amdgpu_init_lvl_id {
847 	enum amdgpu_init_lvl_id level;
872 	enum amd_asic_type		asic_type;
1128 	enum pp_mp1_state               mp1_state;
1297 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1578 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1610 						 enum amdgpu_ss ss_state) { return 0; }  in amdgpu_acpi_smart_shift_update()
1637 			       enum amd_clockgating_state state);
1639 			       enum amd_powergating_state state);
1664 			   enum amdgpu_init_lvl_id lvl);