1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2008 - 2013 Xilinx, Inc.
31 #define XGPIO_GIER_IE		BIT(31)
45  * struct xgpio_instance - Stores information about GPIO device
62 	DECLARE_BITMAP(map, 64);
63 	DECLARE_BITMAP(state, 64);
64 	DECLARE_BITMAP(last_irq_read, 64);
65 	DECLARE_BITMAP(dir, 64);
68 	DECLARE_BITMAP(enable, 64);
69 	DECLARE_BITMAP(rising_edge, 64);
70 	DECLARE_BITMAP(falling_edge, 64);
82 		return -EINVAL;  in xgpio_regoffset()
86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)  in xgpio_read_ch()  argument
88 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);  in xgpio_read_ch()
91 	bitmap_write(a, value, round_down(bit, 32), 32);  in xgpio_read_ch()
94 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)  in xgpio_write_ch()  argument
96 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);  in xgpio_write_ch()
97 	unsigned long value = bitmap_read(a, round_down(bit, 32), 32);  in xgpio_write_ch()
104 	unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);  in xgpio_read_ch_all()
105 	int bit;  in xgpio_read_ch_all()  local
107 	for (bit = 0; bit <= lastbit ; bit += 32)  in xgpio_read_ch_all()
108 		xgpio_read_ch(chip, reg, bit, a);  in xgpio_read_ch_all()
113 	unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);  in xgpio_write_ch_all()
114 	int bit;  in xgpio_write_ch_all()  local
116 	for (bit = 0; bit <= lastbit ; bit += 32)  in xgpio_write_ch_all()
117 		xgpio_write_ch(chip, reg, bit, a);  in xgpio_write_ch_all()
121  * xgpio_get - Read the specified signal of the GPIO device.
134 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_get()  local
135 	DECLARE_BITMAP(state, 64);  in xgpio_get()
137 	xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);  in xgpio_get()
139 	return test_bit(bit, state);  in xgpio_get()
143  * xgpio_set - Write the specified signal of the GPIO device.
155 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_set()  local
157 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_set()
160 	__assign_bit(bit, chip->state, val);  in xgpio_set()
162 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);  in xgpio_set()
164 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_set()
168  * xgpio_set_multiple - Write the specified signals of the GPIO device.
179 	DECLARE_BITMAP(hw_mask, 64);  in xgpio_set_multiple()
180 	DECLARE_BITMAP(hw_bits, 64);  in xgpio_set_multiple()
181 	DECLARE_BITMAP(state, 64);  in xgpio_set_multiple()
185 	bitmap_scatter(hw_mask, mask, chip->map, 64);  in xgpio_set_multiple()
186 	bitmap_scatter(hw_bits, bits, chip->map, 64);  in xgpio_set_multiple()
188 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_set_multiple()
190 	bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);  in xgpio_set_multiple()
194 	bitmap_copy(chip->state, state, 64);  in xgpio_set_multiple()
196 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_set_multiple()
200  * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
205  * 0 - if direction of GPIO signals is set as input
212 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_dir_in()  local
214 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_dir_in()
216 	/* Set the GPIO bit in shadow register and set direction as input */  in xgpio_dir_in()
217 	__set_bit(bit, chip->dir);  in xgpio_dir_in()
218 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);  in xgpio_dir_in()
220 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_dir_in()
226  * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
241 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_dir_out()  local
243 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_dir_out()
246 	__assign_bit(bit, chip->state, val);  in xgpio_dir_out()
247 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);  in xgpio_dir_out()
249 	/* Clear the GPIO bit in shadow register and set direction as output */  in xgpio_dir_out()
250 	__clear_bit(bit, chip->dir);  in xgpio_dir_out()
251 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);  in xgpio_dir_out()
253 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_dir_out()
259  * xgpio_save_regs - Set initial values of GPIO pins
264 	xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);  in xgpio_save_regs()
265 	xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);  in xgpio_save_regs()
272 	ret = pm_runtime_get_sync(chip->parent);  in xgpio_request()
282 	pm_runtime_put(chip->parent);  in xgpio_free()
288 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in xgpio_suspend()
302  * xgpio_remove - Remove method for the GPIO device.
311 	pm_runtime_get_sync(&pdev->dev);  in xgpio_remove()
312 	pm_runtime_put_noidle(&pdev->dev);  in xgpio_remove()
313 	pm_runtime_disable(&pdev->dev);  in xgpio_remove()
317  * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
329 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in xgpio_resume()
346 	clk_disable(gpio->clk);  in xgpio_runtime_suspend()
355 	return clk_enable(gpio->clk);  in xgpio_runtime_resume()
365  * xgpio_irq_mask - Write the specified signal of the GPIO device.
373 	unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;  in xgpio_irq_mask()  local
374 	u32 mask = BIT(bit / 32), temp;  in xgpio_irq_mask()
376 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_irq_mask()
378 	__clear_bit(bit, chip->enable);  in xgpio_irq_mask()
380 	enable = bitmap_read(chip->enable, round_down(bit, 32), 32);  in xgpio_irq_mask()
383 		temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);  in xgpio_irq_mask()
385 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);  in xgpio_irq_mask()
387 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_irq_mask()
389 	gpiochip_disable_irq(&chip->gc, irq_offset);  in xgpio_irq_mask()
393  * xgpio_irq_unmask - Write the specified signal of the GPIO device.
401 	unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;  in xgpio_irq_unmask()  local
402 	u32 mask = BIT(bit / 32), val;  in xgpio_irq_unmask()
404 	gpiochip_enable_irq(&chip->gc, irq_offset);  in xgpio_irq_unmask()
406 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_irq_unmask()
408 	enable = bitmap_read(chip->enable, round_down(bit, 32), 32);  in xgpio_irq_unmask()
410 		/* Clear any existing per-channel interrupts */  in xgpio_irq_unmask()
411 		val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_irq_unmask()
413 		xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);  in xgpio_irq_unmask()
416 		xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);  in xgpio_irq_unmask()
419 		val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);  in xgpio_irq_unmask()
421 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);  in xgpio_irq_unmask()
424 	__set_bit(bit, chip->enable);  in xgpio_irq_unmask()
426 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_irq_unmask()
430  * xgpio_set_irq_type - Write the specified signal of the GPIO device.
435  * 0 if interrupt type is supported otherwise -EINVAL
441 	unsigned long bit = find_nth_bit(chip->map, 64, irq_offset);  in xgpio_set_irq_type()  local
451 		__set_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
452 		__set_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
455 		__set_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
456 		__clear_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
459 		__clear_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
460 		__set_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
463 		return -EINVAL;  in xgpio_set_irq_type()
471  * xgpio_irqhandler - Gpio interrupt service routine
477 	struct gpio_chip *gc = &chip->gc;  in xgpio_irqhandler()
479 	DECLARE_BITMAP(rising, 64);  in xgpio_irqhandler()
480 	DECLARE_BITMAP(falling, 64);  in xgpio_irqhandler()
481 	DECLARE_BITMAP(hw, 64);  in xgpio_irqhandler()
482 	DECLARE_BITMAP(sw, 64);  in xgpio_irqhandler()
486 	status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_irqhandler()
487 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);  in xgpio_irqhandler()
491 	raw_spin_lock(&chip->gpio_lock);  in xgpio_irqhandler()
495 	bitmap_complement(rising, chip->last_irq_read, 64);  in xgpio_irqhandler()
496 	bitmap_and(rising, rising, hw, 64);  in xgpio_irqhandler()
497 	bitmap_and(rising, rising, chip->enable, 64);  in xgpio_irqhandler()
498 	bitmap_and(rising, rising, chip->rising_edge, 64);  in xgpio_irqhandler()
500 	bitmap_complement(falling, hw, 64);  in xgpio_irqhandler()
501 	bitmap_and(falling, falling, chip->last_irq_read, 64);  in xgpio_irqhandler()
502 	bitmap_and(falling, falling, chip->enable, 64);  in xgpio_irqhandler()
503 	bitmap_and(falling, falling, chip->falling_edge, 64);  in xgpio_irqhandler()
505 	bitmap_copy(chip->last_irq_read, hw, 64);  in xgpio_irqhandler()
506 	bitmap_or(hw, rising, falling, 64);  in xgpio_irqhandler()
508 	raw_spin_unlock(&chip->gpio_lock);  in xgpio_irqhandler()
510 	dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);  in xgpio_irqhandler()
512 	bitmap_gather(sw, hw, chip->map, 64);  in xgpio_irqhandler()
513 	for_each_set_bit(irq_offset, sw, 64)  in xgpio_irqhandler()
514 		generic_handle_domain_irq(gc->irq.domain, irq_offset);  in xgpio_irqhandler()
520 	.name = "gpio-xilinx",
530  * xgpio_probe - Probe method for the GPIO device.
539 	struct device *dev = &pdev->dev;  in xgpio_probe()
551 		return -ENOMEM;  in xgpio_probe()
555 	/* First, check if the device is dual-channel */  in xgpio_probe()
556 	device_property_read_u32(dev, "xlnx,is-dual", &is_dual);  in xgpio_probe()
564 	device_property_read_u32(dev, "xlnx,dout-default", &state[0]);  in xgpio_probe()
565 	device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]);  in xgpio_probe()
567 	bitmap_from_arr32(chip->state, state, 64);  in xgpio_probe()
570 	device_property_read_u32(dev, "xlnx,tri-default", &dir[0]);  in xgpio_probe()
571 	device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]);  in xgpio_probe()
573 	bitmap_from_arr32(chip->dir, dir, 64);  in xgpio_probe()
579 	if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0]))  in xgpio_probe()
583 		return -EINVAL;  in xgpio_probe()
585 	if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1]))  in xgpio_probe()
589 		return -EINVAL;  in xgpio_probe()
592 	bitmap_set(chip->map,  0, width[0]);  in xgpio_probe()
593 	bitmap_set(chip->map, 32, width[1]);  in xgpio_probe()
595 	raw_spin_lock_init(&chip->gpio_lock);  in xgpio_probe()
597 	chip->gc.base = -1;  in xgpio_probe()
598 	chip->gc.ngpio = bitmap_weight(chip->map, 64);  in xgpio_probe()
599 	chip->gc.parent = dev;  in xgpio_probe()
600 	chip->gc.direction_input = xgpio_dir_in;  in xgpio_probe()
601 	chip->gc.direction_output = xgpio_dir_out;  in xgpio_probe()
602 	chip->gc.get = xgpio_get;  in xgpio_probe()
603 	chip->gc.set = xgpio_set;  in xgpio_probe()
604 	chip->gc.request = xgpio_request;  in xgpio_probe()
605 	chip->gc.free = xgpio_free;  in xgpio_probe()
606 	chip->gc.set_multiple = xgpio_set_multiple;  in xgpio_probe()
608 	chip->gc.label = dev_name(dev);  in xgpio_probe()
610 	chip->regs = devm_platform_ioremap_resource(pdev, 0);  in xgpio_probe()
611 	if (IS_ERR(chip->regs)) {  in xgpio_probe()
613 		return PTR_ERR(chip->regs);  in xgpio_probe()
616 	chip->clk = devm_clk_get_optional_enabled(dev, NULL);  in xgpio_probe()
617 	if (IS_ERR(chip->clk))  in xgpio_probe()
618 		return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n");  in xgpio_probe()
626 	chip->irq = platform_get_irq_optional(pdev, 0);  in xgpio_probe()
627 	if (chip->irq <= 0)  in xgpio_probe()
630 	/* Disable per-channel interrupts */  in xgpio_probe()
631 	xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);  in xgpio_probe()
632 	/* Clear any existing per-channel interrupts */  in xgpio_probe()
633 	temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_probe()
634 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);  in xgpio_probe()
636 	xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);  in xgpio_probe()
638 	girq = &chip->gc.irq;  in xgpio_probe()
640 	girq->parent_handler = xgpio_irqhandler;  in xgpio_probe()
641 	girq->num_parents = 1;  in xgpio_probe()
642 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in xgpio_probe()
644 	if (!girq->parents) {  in xgpio_probe()
645 		status = -ENOMEM;  in xgpio_probe()
648 	girq->parents[0] = chip->irq;  in xgpio_probe()
649 	girq->default_type = IRQ_TYPE_NONE;  in xgpio_probe()
650 	girq->handler = handle_bad_irq;  in xgpio_probe()
653 	status = devm_gpiochip_add_data(dev, &chip->gc, chip);  in xgpio_probe()
669 	{ .compatible = "xlnx,xps-gpio-1.00.a", },
679 			.name = "gpio-xilinx",