Lines Matching full:gpio
10 #include <linux/gpio/aspeed.h>
11 #include <linux/gpio/driver.h>
26 * These two headers aren't meant to be used by GPIO drivers. We need
31 #include <linux/gpio/consumer.h>
76 * represents disabled debouncing for the GPIO. Any other value for an element
110 * line even when the GPIO is configured as an output. Since
224 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset,
226 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset,
228 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset,
230 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner);
231 void (*privilege_init)(struct aspeed_gpio *gpio);
232 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset);
233 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset);
256 static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio, in aspeed_gpio_g4_bank_reg() argument
262 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in aspeed_gpio_g4_bank_reg()
264 return gpio->base + bank->rdata_reg; in aspeed_gpio_g4_bank_reg()
266 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in aspeed_gpio_g4_bank_reg()
268 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in aspeed_gpio_g4_bank_reg()
270 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in aspeed_gpio_g4_bank_reg()
272 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in aspeed_gpio_g4_bank_reg()
274 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in aspeed_gpio_g4_bank_reg()
276 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in aspeed_gpio_g4_bank_reg()
278 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in aspeed_gpio_g4_bank_reg()
280 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in aspeed_gpio_g4_bank_reg()
282 return gpio->base + bank->tolerance_regs; in aspeed_gpio_g4_bank_reg()
284 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in aspeed_gpio_g4_bank_reg()
286 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in aspeed_gpio_g4_bank_reg()
342 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument
344 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
355 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument
357 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio()
359 if (offset >= gpio->chip.ngpio) in have_gpio()
365 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument
367 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_input()
375 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) in have_output() argument
377 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_output()
382 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) in aspeed_gpio_change_cmd_source() argument
384 if (gpio->config->llops->privilege_ctrl) in aspeed_gpio_change_cmd_source()
385 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); in aspeed_gpio_change_cmd_source()
388 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, in aspeed_gpio_copro_request() argument
391 if (gpio->config->llops->copro_request) in aspeed_gpio_copro_request()
392 return gpio->config->llops->copro_request(gpio, offset); in aspeed_gpio_copro_request()
397 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, in aspeed_gpio_copro_release() argument
400 if (gpio->config->llops->copro_release) in aspeed_gpio_copro_release()
401 gpio->config->llops->copro_release(gpio, offset); in aspeed_gpio_copro_release()
404 static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio) in aspeed_gpio_support_copro() argument
406 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && in aspeed_gpio_support_copro()
407 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; in aspeed_gpio_support_copro()
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_get() local
414 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in aspeed_gpio_get()
420 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in __aspeed_gpio_set() local
422 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); in __aspeed_gpio_set()
424 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in __aspeed_gpio_set()
429 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_set() local
432 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_set()
434 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set()
439 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set()
446 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_dir_in() local
449 if (!have_input(gpio, offset)) in aspeed_gpio_dir_in()
452 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_dir_in()
454 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_in()
455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); in aspeed_gpio_dir_in()
457 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_in()
465 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_dir_out() local
468 if (!have_output(gpio, offset)) in aspeed_gpio_dir_out()
471 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_dir_out()
473 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_out()
475 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); in aspeed_gpio_dir_out()
478 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_out()
485 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_get_direction() local
488 if (!have_input(gpio, offset)) in aspeed_gpio_get_direction()
491 if (!have_output(gpio, offset)) in aspeed_gpio_get_direction()
494 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_get_direction()
496 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); in aspeed_gpio_get_direction()
502 struct aspeed_gpio **gpio, in irqd_to_aspeed_gpio_data() argument
515 *gpio = internal; in irqd_to_aspeed_gpio_data()
522 struct aspeed_gpio *gpio; in aspeed_gpio_irq_ack() local
526 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_irq_ack()
530 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_irq_ack()
532 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_ack()
534 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); in aspeed_gpio_irq_ack()
537 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_ack()
542 struct aspeed_gpio *gpio; in aspeed_gpio_irq_set_mask() local
546 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_irq_set_mask()
552 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
554 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_irq_set_mask()
556 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_set_mask()
558 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); in aspeed_gpio_irq_set_mask()
561 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_set_mask()
565 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
584 struct aspeed_gpio *gpio; in aspeed_gpio_set_type() local
588 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_set_type()
613 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { in aspeed_gpio_set_type()
614 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set_type()
616 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, in aspeed_gpio_set_type()
618 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, in aspeed_gpio_set_type()
620 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, in aspeed_gpio_set_type()
624 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set_type()
638 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_irq_handler() local
642 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
644 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); in aspeed_gpio_irq_handler()
657 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_init_irq_valid_mask() local
658 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
664 /* Pretty crummy approach, but similar to GPIO core */ in aspeed_init_irq_valid_mask()
668 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
681 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_reset_tolerance() local
684 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_reset_tolerance()
686 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_reset_tolerance()
688 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); in aspeed_gpio_reset_tolerance()
691 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_reset_tolerance()
709 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, in usecs_to_cycles() argument
716 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
732 /* Call under gpio->lock */
733 static int register_allocated_timer(struct aspeed_gpio *gpio, in register_allocated_timer() argument
736 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
738 offset, gpio->offset_timer[offset])) in register_allocated_timer()
741 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
745 gpio->offset_timer[offset] = timer; in register_allocated_timer()
746 gpio->timer_users[timer]++; in register_allocated_timer()
751 /* Call under gpio->lock */
752 static int unregister_allocated_timer(struct aspeed_gpio *gpio, in unregister_allocated_timer() argument
755 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
759 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
761 gpio->offset_timer[offset])) in unregister_allocated_timer()
764 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
765 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
770 /* Call under gpio->lock */
771 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, in timer_allocation_registered() argument
774 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
777 /* Call under gpio->lock */
778 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, in configure_timer() argument
784 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); in configure_timer()
785 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); in configure_timer()
791 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in enable_debounce() local
796 if (!gpio->clk) in enable_debounce()
799 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); in enable_debounce()
802 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
806 guard(raw_spinlock_irqsave)(&gpio->lock); in enable_debounce()
808 if (timer_allocation_registered(gpio, offset)) { in enable_debounce()
809 rc = unregister_allocated_timer(gpio, offset); in enable_debounce()
815 for (i = 1; i < gpio->config->debounce_timers_num; i++) { in enable_debounce()
818 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
823 if (i == gpio->config->debounce_timers_num) { in enable_debounce()
830 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
831 if (gpio->timer_users[j] == 0) in enable_debounce()
835 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
848 configure_timer(gpio, offset, 0); in enable_debounce()
854 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
860 register_allocated_timer(gpio, offset, i); in enable_debounce()
861 configure_timer(gpio, offset, i); in enable_debounce()
868 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in disable_debounce() local
871 guard(raw_spinlock_irqsave)(&gpio->lock); in disable_debounce()
873 rc = unregister_allocated_timer(gpio, offset); in disable_debounce()
875 configure_timer(gpio, offset, 0); in disable_debounce()
883 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in set_debounce() local
885 if (!have_debounce(gpio, offset)) in set_debounce()
918 * the coprocessor for shared GPIO banks
932 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
935 * @desc: The GPIO to be marked
936 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
937 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
938 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
944 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_copro_grab_gpio() local
948 if (!aspeed_gpio_support_copro(gpio)) in aspeed_gpio_copro_grab_gpio()
951 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
952 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
953 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
955 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
959 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_copro_grab_gpio()
962 if (gpio->cf_copro_bankmap[bindex] == 0xff) in aspeed_gpio_copro_grab_gpio()
965 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
968 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
969 aspeed_gpio_change_cmd_source(gpio, offset, in aspeed_gpio_copro_grab_gpio()
983 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
984 * @desc: The GPIO to be marked
989 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_copro_release_gpio() local
992 if (!aspeed_gpio_support_copro(gpio)) in aspeed_gpio_copro_release_gpio()
995 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
998 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
1002 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_copro_release_gpio()
1005 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1008 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1011 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1012 aspeed_gpio_change_cmd_source(gpio, offset, in aspeed_gpio_copro_release_gpio()
1021 struct aspeed_gpio *gpio; in aspeed_gpio_irq_print_chip() local
1024 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_irq_print_chip()
1028 seq_puts(p, dev_name(gpio->dev)); in aspeed_gpio_irq_print_chip()
1041 static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g4_reg_bit_set() argument
1045 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bit_set()
1049 temp = gpio->dcache[GPIO_BANK(offset)]; in aspeed_g4_reg_bit_set()
1059 gpio->dcache[GPIO_BANK(offset)] = temp; in aspeed_g4_reg_bit_set()
1063 static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g4_reg_bit_get() argument
1067 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bit_get()
1072 static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g4_reg_bank_get() argument
1076 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bank_get()
1084 static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) in aspeed_g4_privilege_ctrl() argument
1091 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1))); in aspeed_g4_privilege_ctrl()
1093 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0))); in aspeed_g4_privilege_ctrl()
1096 static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio) in aspeed_g4_privilege_init() argument
1101 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { in aspeed_g4_privilege_init()
1102 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1103 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1104 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1105 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1109 static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset) in aspeed_g4_copro_request() argument
1111 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_request()
1113 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_request()
1122 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM); in aspeed_g4_copro_request()
1125 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); in aspeed_g4_copro_request()
1130 static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset) in aspeed_g4_copro_release() argument
1132 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_release()
1134 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_release()
1140 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE); in aspeed_g4_copro_release()
1156 static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g7_reg_bit_set() argument
1160 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_set()
1169 static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g7_reg_bit_get() argument
1175 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_get()
1185 static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g7_reg_bank_get() argument
1191 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); in aspeed_g7_reg_bank_get()
1218 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1223 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1236 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1242 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1277 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */
1285 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH)
1299 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1300 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1301 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1302 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, },
1311 struct aspeed_gpio *gpio; in aspeed_gpio_probe() local
1315 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1316 if (!gpio) in aspeed_gpio_probe()
1319 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1320 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1321 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1323 gpio->dev = &pdev->dev; in aspeed_gpio_probe()
1325 raw_spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1331 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in aspeed_gpio_probe()
1332 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1335 gpio->clk = NULL; in aspeed_gpio_probe()
1338 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1340 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || in aspeed_gpio_probe()
1341 !gpio->config->llops->reg_bank_get) in aspeed_gpio_probe()
1344 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1346 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1348 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1349 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1350 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1351 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1352 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1353 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1354 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1355 gpio->chip.set_rv = aspeed_gpio_set; in aspeed_gpio_probe()
1356 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1357 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1358 gpio->chip.base = -1; in aspeed_gpio_probe()
1360 if (gpio->config->require_dcache) { in aspeed_gpio_probe()
1362 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1363 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); in aspeed_gpio_probe()
1364 if (!gpio->dcache) in aspeed_gpio_probe()
1370 gpio->dcache[i] = in aspeed_gpio_probe()
1371 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); in aspeed_gpio_probe()
1374 if (gpio->config->llops->privilege_init) in aspeed_gpio_probe()
1375 gpio->config->llops->privilege_init(gpio); in aspeed_gpio_probe()
1381 gpio->irq = irq; in aspeed_gpio_probe()
1382 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1390 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1395 gpio->offset_timer = in aspeed_gpio_probe()
1396 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1397 if (!gpio->offset_timer) in aspeed_gpio_probe()
1400 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()
1417 MODULE_DESCRIPTION("Aspeed GPIO Driver");