Lines Matching +full:four +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
36 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
56 unsigned int bank; member
74 * The @timer_users has four elements but the first element is unused. This is
257 const struct aspeed_gpio_bank *bank, in aspeed_gpio_g4_bank_reg() argument
262 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in aspeed_gpio_g4_bank_reg()
264 return gpio->base + bank->rdata_reg; in aspeed_gpio_g4_bank_reg()
266 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in aspeed_gpio_g4_bank_reg()
268 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in aspeed_gpio_g4_bank_reg()
270 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in aspeed_gpio_g4_bank_reg()
272 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in aspeed_gpio_g4_bank_reg()
274 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in aspeed_gpio_g4_bank_reg()
276 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in aspeed_gpio_g4_bank_reg()
278 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in aspeed_gpio_g4_bank_reg()
280 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in aspeed_gpio_g4_bank_reg()
282 return gpio->base + bank->tolerance_regs; in aspeed_gpio_g4_bank_reg()
284 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in aspeed_gpio_g4_bank_reg()
286 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in aspeed_gpio_g4_bank_reg()
330 unsigned int bank = GPIO_BANK(offset); in to_bank() local
332 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); in to_bank()
333 return &aspeed_gpio_banks[bank]; in to_bank()
338 return !(props->input || props->output); in is_bank_props_sentinel()
344 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
347 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
359 if (offset >= gpio->chip.ngpio) in have_gpio()
362 return (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
369 return !props || (props->input & GPIO_BIT(offset)); in have_input()
379 return !props || (props->output & GPIO_BIT(offset)); in have_output()
384 if (gpio->config->llops->privilege_ctrl) in aspeed_gpio_change_cmd_source()
385 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); in aspeed_gpio_change_cmd_source()
391 if (gpio->config->llops->copro_request) in aspeed_gpio_copro_request()
392 return gpio->config->llops->copro_request(gpio, offset); in aspeed_gpio_copro_request()
400 if (gpio->config->llops->copro_release) in aspeed_gpio_copro_release()
401 gpio->config->llops->copro_release(gpio, offset); in aspeed_gpio_copro_release()
406 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && in aspeed_gpio_support_copro()
407 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; in aspeed_gpio_support_copro()
414 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in aspeed_gpio_get()
422 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); in __aspeed_gpio_set()
424 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in __aspeed_gpio_set()
432 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_set()
450 return -ENOTSUPP; in aspeed_gpio_dir_in()
452 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_dir_in()
455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); in aspeed_gpio_dir_in()
469 return -ENOTSUPP; in aspeed_gpio_dir_out()
471 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_dir_out()
475 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); in aspeed_gpio_dir_out()
494 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_get_direction()
496 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); in aspeed_gpio_get_direction()
513 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
530 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_irq_ack()
534 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); in aspeed_gpio_irq_ack()
552 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
554 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_irq_set_mask()
558 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); in aspeed_gpio_irq_set_mask()
565 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
590 return -EINVAL; in aspeed_gpio_set_type()
610 return -EINVAL; in aspeed_gpio_set_type()
613 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { in aspeed_gpio_set_type()
616 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, in aspeed_gpio_set_type()
618 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, in aspeed_gpio_set_type()
620 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, in aspeed_gpio_set_type()
642 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
644 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); in aspeed_gpio_irq_handler()
647 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
658 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
662 const unsigned long int input = props->input; in aspeed_init_irq_valid_mask()
666 unsigned int i = props->bank * 32 + offset; in aspeed_init_irq_valid_mask()
668 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
684 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_reset_tolerance()
688 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); in aspeed_gpio_reset_tolerance()
699 return -ENODEV; in aspeed_gpio_request()
716 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
718 return -ENOTSUPP; in usecs_to_cycles()
724 return -ERANGE; in usecs_to_cycles()
732 /* Call under gpio->lock */
736 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
738 offset, gpio->offset_timer[offset])) in register_allocated_timer()
739 return -EINVAL; in register_allocated_timer()
741 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
743 return -EPERM; in register_allocated_timer()
745 gpio->offset_timer[offset] = timer; in register_allocated_timer()
746 gpio->timer_users[timer]++; in register_allocated_timer()
751 /* Call under gpio->lock */
755 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
757 return -EINVAL; in unregister_allocated_timer()
759 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
761 gpio->offset_timer[offset])) in unregister_allocated_timer()
762 return -EINVAL; in unregister_allocated_timer()
764 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
765 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
770 /* Call under gpio->lock */
774 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
777 /* Call under gpio->lock */
784 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); in configure_timer()
785 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); in configure_timer()
796 if (!gpio->clk) in enable_debounce()
797 return -EINVAL; in enable_debounce()
801 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
802 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
806 guard(raw_spinlock_irqsave)(&gpio->lock); in enable_debounce()
815 for (i = 1; i < gpio->config->debounce_timers_num; i++) { in enable_debounce()
818 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
823 if (i == gpio->config->debounce_timers_num) { in enable_debounce()
830 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
831 if (gpio->timer_users[j] == 0) in enable_debounce()
835 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
836 dev_warn(chip->parent, in enable_debounce()
840 rc = -EPERM; in enable_debounce()
854 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
858 return -EINVAL; in enable_debounce()
871 guard(raw_spinlock_irqsave)(&gpio->lock); in disable_debounce()
886 return -ENOTSUPP; in set_debounce()
908 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
909 return -ENOTSUPP; in aspeed_gpio_set_config()
913 return -ENOTSUPP; in aspeed_gpio_set_config()
917 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
932 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
933 * bank gets marked and any access from the ARM will
936 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
937 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
938 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
946 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_grab_gpio() local
949 return -EOPNOTSUPP; in aspeed_gpio_copro_grab_gpio()
951 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
952 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
953 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
954 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
955 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
956 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
959 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_copro_grab_gpio()
962 if (gpio->cf_copro_bankmap[bindex] == 0xff) in aspeed_gpio_copro_grab_gpio()
963 return -EIO; in aspeed_gpio_copro_grab_gpio()
965 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
968 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
973 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
975 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
983 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
993 return -EOPNOTSUPP; in aspeed_gpio_copro_release_gpio()
995 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
996 return -ENXIO; in aspeed_gpio_copro_release_gpio()
998 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
999 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1002 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_gpio_copro_release_gpio()
1005 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1006 return -EIO; in aspeed_gpio_copro_release_gpio()
1008 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1011 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1028 seq_puts(p, dev_name(gpio->dev)); in aspeed_gpio_irq_print_chip()
1044 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_g4_reg_bit_set() local
1045 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bit_set()
1049 temp = gpio->dcache[GPIO_BANK(offset)]; in aspeed_g4_reg_bit_set()
1059 gpio->dcache[GPIO_BANK(offset)] = temp; in aspeed_g4_reg_bit_set()
1066 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_g4_reg_bit_get() local
1067 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bit_get()
1075 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_g4_reg_bank_get() local
1076 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bank_get()
1081 return -EOPNOTSUPP; in aspeed_g4_reg_bank_get()
1101 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { in aspeed_g4_privilege_init()
1111 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_request()
1113 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_request()
1115 if (!copro_ops->request_access) in aspeed_g4_copro_request()
1119 copro_ops->request_access(copro_data); in aspeed_g4_copro_request()
1125 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); in aspeed_g4_copro_request()
1132 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_release()
1134 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_release()
1136 if (!copro_ops->release_access) in aspeed_g4_copro_release()
1143 copro_ops->release_access(copro_data); in aspeed_g4_copro_release()
1160 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_set()
1175 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_get()
1191 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); in aspeed_g7_reg_bank_get()
1194 return -EOPNOTSUPP; in aspeed_g7_reg_bank_get()
1218 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1223 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1236 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1242 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1277 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */
1285 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH)
1299 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1300 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1301 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1302 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, },
1315 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1317 return -ENOMEM; in aspeed_gpio_probe()
1319 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1320 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1321 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1323 gpio->dev = &pdev->dev; in aspeed_gpio_probe()
1325 raw_spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1327 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1329 return -EINVAL; in aspeed_gpio_probe()
1331 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in aspeed_gpio_probe()
1332 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1333 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1335 gpio->clk = NULL; in aspeed_gpio_probe()
1338 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1340 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || in aspeed_gpio_probe()
1341 !gpio->config->llops->reg_bank_get) in aspeed_gpio_probe()
1342 return -EINVAL; in aspeed_gpio_probe()
1344 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1345 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); in aspeed_gpio_probe()
1346 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1348 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1349 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1350 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1351 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1352 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1353 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1354 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1355 gpio->chip.set_rv = aspeed_gpio_set; in aspeed_gpio_probe()
1356 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1357 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1358 gpio->chip.base = -1; in aspeed_gpio_probe()
1360 if (gpio->config->require_dcache) { in aspeed_gpio_probe()
1362 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1363 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); in aspeed_gpio_probe()
1364 if (!gpio->dcache) in aspeed_gpio_probe()
1365 return -ENOMEM; in aspeed_gpio_probe()
1370 gpio->dcache[i] = in aspeed_gpio_probe()
1371 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); in aspeed_gpio_probe()
1374 if (gpio->config->llops->privilege_init) in aspeed_gpio_probe()
1375 gpio->config->llops->privilege_init(gpio); in aspeed_gpio_probe()
1381 gpio->irq = irq; in aspeed_gpio_probe()
1382 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1385 girq->parent_handler = aspeed_gpio_irq_handler; in aspeed_gpio_probe()
1386 girq->num_parents = 1; in aspeed_gpio_probe()
1387 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); in aspeed_gpio_probe()
1388 if (!girq->parents) in aspeed_gpio_probe()
1389 return -ENOMEM; in aspeed_gpio_probe()
1390 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1391 girq->default_type = IRQ_TYPE_NONE; in aspeed_gpio_probe()
1392 girq->handler = handle_bad_irq; in aspeed_gpio_probe()
1393 girq->init_valid_mask = aspeed_init_irq_valid_mask; in aspeed_gpio_probe()
1395 gpio->offset_timer = in aspeed_gpio_probe()
1396 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1397 if (!gpio->offset_timer) in aspeed_gpio_probe()
1398 return -ENOMEM; in aspeed_gpio_probe()
1400 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()