Lines Matching +full:input +full:- +full:ngpios
1 // SPDX-License-Identifier: GPL-2.0-or-later
50 * Note: The "value" register returns the input value when the GPIO is
51 * configured as an input.
111 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
113 return gpio->base + bank->rdata_reg; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
121 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
123 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
125 return gpio->base + bank->tolerance_regs; in bank_reg()
147 unsigned long *valid_mask, unsigned int ngpios) in aspeed_sgpio_init_valid_mask() argument
149 bitmap_set(valid_mask, 0, ngpios); in aspeed_sgpio_init_valid_mask()
154 unsigned long *valid_mask, unsigned int ngpios) in aspeed_sgpio_irq_init_valid_mask() argument
158 /* input GPIOs are even bits */ in aspeed_sgpio_irq_init_valid_mask()
159 for (i = 0; i < ngpios; i++) { in aspeed_sgpio_irq_init_valid_mask()
177 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_sgpio_get()
193 return -EINVAL; in sgpio_set_value()
216 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_sgpio_set()
223 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; in aspeed_sgpio_dir_in()
232 * error-out in sgpio_set_value if this isn't an output GPIO */ in aspeed_sgpio_dir_out()
234 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_sgpio_dir_out()
274 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_sgpio_irq_ack()
292 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_sgpio_irq_set_mask()
294 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { in aspeed_sgpio_irq_set_mask()
306 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_sgpio_irq_set_mask()
353 return -EINVAL; in aspeed_sgpio_set_type()
356 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { in aspeed_sgpio_set_type()
394 generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); in aspeed_sgpio_irq_handler()
408 seq_puts(p, dev_name(gpio->dev)); in aspeed_sgpio_irq_print_chip()
432 gpio->irq = rc; in aspeed_sgpio_setup_irqs()
443 irq = &gpio->chip.irq; in aspeed_sgpio_setup_irqs()
445 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask; in aspeed_sgpio_setup_irqs()
446 irq->handler = handle_bad_irq; in aspeed_sgpio_setup_irqs()
447 irq->default_type = IRQ_TYPE_NONE; in aspeed_sgpio_setup_irqs()
448 irq->parent_handler = aspeed_sgpio_irq_handler; in aspeed_sgpio_setup_irqs()
449 irq->parent_handler_data = gpio; in aspeed_sgpio_setup_irqs()
450 irq->parents = &gpio->irq; in aspeed_sgpio_setup_irqs()
451 irq->num_parents = 1; in aspeed_sgpio_setup_irqs()
456 /* set falling or level-low irq */ in aspeed_sgpio_setup_irqs()
480 guard(raw_spinlock_irqsave)(&gpio->lock); in aspeed_sgpio_reset_tolerance()
503 return -ENOTSUPP; in aspeed_sgpio_set_config()
511 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
512 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
513 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
527 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_sgpio_probe()
529 return -ENOMEM; in aspeed_sgpio_probe()
531 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_sgpio_probe()
532 if (IS_ERR(gpio->base)) in aspeed_sgpio_probe()
533 return PTR_ERR(gpio->base); in aspeed_sgpio_probe()
535 gpio->dev = &pdev->dev; in aspeed_sgpio_probe()
537 pdata = device_get_match_data(&pdev->dev); in aspeed_sgpio_probe()
539 return -EINVAL; in aspeed_sgpio_probe()
541 pin_mask = pdata->pin_mask; in aspeed_sgpio_probe()
543 rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios); in aspeed_sgpio_probe()
545 dev_err(&pdev->dev, "Could not read ngpios property\n"); in aspeed_sgpio_probe()
546 return -EINVAL; in aspeed_sgpio_probe()
548 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n", in aspeed_sgpio_probe()
550 return -EINVAL; in aspeed_sgpio_probe()
553 rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq); in aspeed_sgpio_probe()
555 dev_err(&pdev->dev, "Could not read bus-frequency property\n"); in aspeed_sgpio_probe()
556 return -EINVAL; in aspeed_sgpio_probe()
559 gpio->pclk = devm_clk_get(&pdev->dev, NULL); in aspeed_sgpio_probe()
560 if (IS_ERR(gpio->pclk)) { in aspeed_sgpio_probe()
561 dev_err(&pdev->dev, "devm_clk_get failed\n"); in aspeed_sgpio_probe()
562 return PTR_ERR(gpio->pclk); in aspeed_sgpio_probe()
565 apb_freq = clk_get_rate(gpio->pclk); in aspeed_sgpio_probe()
574 * GPIO254[31:16] = PCLK / (frequency * 2) - 1 in aspeed_sgpio_probe()
577 return -EINVAL; in aspeed_sgpio_probe()
579 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; in aspeed_sgpio_probe()
581 if (sgpio_clk_div > (1 << 16) - 1) in aspeed_sgpio_probe()
582 return -EINVAL; in aspeed_sgpio_probe()
586 ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL); in aspeed_sgpio_probe()
588 raw_spin_lock_init(&gpio->lock); in aspeed_sgpio_probe()
590 gpio->chip.parent = &pdev->dev; in aspeed_sgpio_probe()
591 gpio->chip.ngpio = nr_gpios * 2; in aspeed_sgpio_probe()
592 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask; in aspeed_sgpio_probe()
593 gpio->chip.direction_input = aspeed_sgpio_dir_in; in aspeed_sgpio_probe()
594 gpio->chip.direction_output = aspeed_sgpio_dir_out; in aspeed_sgpio_probe()
595 gpio->chip.get_direction = aspeed_sgpio_get_direction; in aspeed_sgpio_probe()
596 gpio->chip.request = NULL; in aspeed_sgpio_probe()
597 gpio->chip.free = NULL; in aspeed_sgpio_probe()
598 gpio->chip.get = aspeed_sgpio_get; in aspeed_sgpio_probe()
599 gpio->chip.set_rv = aspeed_sgpio_set; in aspeed_sgpio_probe()
600 gpio->chip.set_config = aspeed_sgpio_set_config; in aspeed_sgpio_probe()
601 gpio->chip.label = dev_name(&pdev->dev); in aspeed_sgpio_probe()
602 gpio->chip.base = -1; in aspeed_sgpio_probe()
606 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_sgpio_probe()