Lines Matching +full:ras +full:- +full:to +full:- +full:cas
18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
23 * 4 dimm's, each with up to 8GB.
84 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
89 /* Non-fatal error register */
141 * Error masks are according with Table 5-17 of i5400 datasheet
145 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
146 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
149 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
151 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
153 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
155 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
156 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
158 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
159 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
160 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
161 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
163 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
165 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
167 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
172 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
173 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
177 * Names to translate bit error into something useful
180 [0] = "Memory Write error on non-redundant retry",
181 [1] = "Memory or FB-DIMM configuration CRC read error",
184 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
186 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
188 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
190 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
191 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
193 [13] = "FB-DIMM Configuration Write error on first attempt",
194 [14] = "Memory or FB-DIMM configuration CRC read error",
195 [15] = "Channel Failed-Over Occurred",
196 [16] = "Correctable Non-Mirrored Demand Data ECC",
198 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
200 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
202 [22] = "Non-Redundant Fast Reset Timeout",
207 [27] = "DIMM-Spare Copy Completed",
208 [28] = "DIMM-Isolation Completed",
245 /* mask to all non-fatal errors */
263 /* masks for non-fatal error register */
272 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ in from_nf_ferr()
284 * Defines to extract the various fields from the
285 * MTRx - Memory Technology Registers
299 /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
363 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
364 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
371 /* These registers are input ONLY if there was a Non-Rec Error */
372 u16 nrecmema; /* Non-Recoverable Mem log A */
373 u32 nrecmemb; /* Non-Recoverable Mem log B */
377 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
378 5400 better to use an inline function than a macro in this case */
381 return ((info->nrecmema) >> 12) & 0x7; in nrec_bank()
385 return ((info->nrecmema) >> 8) & 0xf; in nrec_rank()
389 return ((info->nrecmema)) & 0xff; in nrec_buf_id()
393 return (info->nrecmemb) >> 31; in nrec_rdwr()
395 /* This applies to both NREC and REC string so it can be used with nrec_rdwr
403 return ((info->nrecmemb) >> 16) & 0x1fff; in nrec_cas()
407 return (info->nrecmemb) & 0xffff; in nrec_ras()
411 return ((info->recmema) >> 12) & 0x7; in rec_bank()
415 return ((info->recmema) >> 8) & 0xf; in rec_rank()
419 return (info->recmemb) >> 31; in rec_rdwr()
423 return ((info->recmemb) >> 16) & 0x1fff; in rec_cas()
427 return (info->recmemb) & 0xffff; in rec_ras()
443 pvt = mci->pvt_info; in i5400_get_error_info()
446 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); in i5400_get_error_info()
456 info->ferr_fat_fbd = value; in i5400_get_error_info()
459 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
460 NERR_FAT_FBD, &info->nerr_fat_fbd); in i5400_get_error_info()
461 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
462 NRECMEMA, &info->nrecmema); in i5400_get_error_info()
463 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
464 NRECMEMB, &info->nrecmemb); in i5400_get_error_info()
467 pci_write_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
470 info->ferr_fat_fbd = 0; in i5400_get_error_info()
471 info->nerr_fat_fbd = 0; in i5400_get_error_info()
472 info->nrecmema = 0; in i5400_get_error_info()
473 info->nrecmemb = 0; in i5400_get_error_info()
476 /* read in the 1st NON-FATAL error register */ in i5400_get_error_info()
477 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); in i5400_get_error_info()
479 /* If there is an error, then read in the 1st NON-FATAL error in i5400_get_error_info()
482 info->ferr_nf_fbd = value; in i5400_get_error_info()
485 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
486 NERR_NF_FBD, &info->nerr_nf_fbd); in i5400_get_error_info()
487 pci_read_config_word(pvt->branchmap_werrors, in i5400_get_error_info()
488 RECMEMA, &info->recmema); in i5400_get_error_info()
489 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
490 RECMEMB, &info->recmemb); in i5400_get_error_info()
491 pci_read_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
492 REDMEMB, &info->redmemb); in i5400_get_error_info()
495 pci_write_config_dword(pvt->branchmap_werrors, in i5400_get_error_info()
498 info->ferr_nf_fbd = 0; in i5400_get_error_info()
499 info->nerr_nf_fbd = 0; in i5400_get_error_info()
500 info->recmema = 0; in i5400_get_error_info()
501 info->recmemb = 0; in i5400_get_error_info()
502 info->redmemb = 0; in i5400_get_error_info()
524 int ras, cas; in i5400_proccess_non_recoverable_info() local
536 type = "NON-FATAL uncorrected"; in i5400_proccess_non_recoverable_info()
538 type = "NON-FATAL recoverable"; in i5400_proccess_non_recoverable_info()
542 branch = extract_fbdchan_indx(info->ferr_fat_fbd); in i5400_proccess_non_recoverable_info()
545 /* Use the NON-Recoverable macros to extract data */ in i5400_proccess_non_recoverable_info()
550 ras = nrec_ras(info); in i5400_proccess_non_recoverable_info()
551 cas = nrec_cas(info); in i5400_proccess_non_recoverable_info()
553 …s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", in i5400_proccess_non_recoverable_info()
555 buf_id, rdwr_str(rdwr), ras, cas); in i5400_proccess_non_recoverable_info()
562 "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", in i5400_proccess_non_recoverable_info()
563 bank, buf_id, ras, cas, allErrors, error_name[errnum]); in i5400_proccess_non_recoverable_info()
566 branch >> 1, -1, rank, in i5400_proccess_non_recoverable_info()
576 * handle the Intel NON-FATAL errors, if any
588 int ras, cas; in i5400_process_nonfatal_error_info() local
592 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); in i5400_process_nonfatal_error_info()
607 branch = extract_fbdchan_indx(info->ferr_nf_fbd); in i5400_process_nonfatal_error_info()
610 if (REC_ECC_LOCATOR_ODD(info->redmemb)) in i5400_process_nonfatal_error_info()
613 /* Convert channel to be based from zero, instead of in i5400_process_nonfatal_error_info()
620 ras = rec_ras(info); in i5400_process_nonfatal_error_info()
621 cas = rec_cas(info); in i5400_process_nonfatal_error_info()
626 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", in i5400_process_nonfatal_error_info()
628 rdwr_str(rdwr), ras, cas); in i5400_process_nonfatal_error_info()
632 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " in i5400_process_nonfatal_error_info()
633 "RAS=%d CAS=%d, CE Err=0x%lx (%s))", in i5400_process_nonfatal_error_info()
634 branch >> 1, bank, rdwr_str(rdwr), ras, cas, in i5400_process_nonfatal_error_info()
648 branch = extract_fbdchan_indx(info->ferr_nf_fbd); in i5400_process_nonfatal_error_info()
651 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", in i5400_process_nonfatal_error_info()
664 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); in i5400_process_error_info()
667 /* now handle any non-fatal errors that occurred */ in i5400_process_error_info()
704 pvt = mci->pvt_info; in i5400_put_devices()
707 pci_dev_put(pvt->branch_1); in i5400_put_devices()
708 pci_dev_put(pvt->branch_0); in i5400_put_devices()
709 pci_dev_put(pvt->fsb_error_regs); in i5400_put_devices()
710 pci_dev_put(pvt->branchmap_werrors); in i5400_put_devices()
715 * device/functions we want to reference for this driver
717 * Need to 'get' device 16 func 1 and func 2
724 pvt = mci->pvt_info; in i5400_get_devices()
725 pvt->branchmap_werrors = NULL; in i5400_get_devices()
726 pvt->fsb_error_regs = NULL; in i5400_get_devices()
727 pvt->branch_0 = NULL; in i5400_get_devices()
728 pvt->branch_1 = NULL; in i5400_get_devices()
730 /* Attempt to 'get' the MCH register we want */ in i5400_get_devices()
744 return -ENODEV; in i5400_get_devices()
748 if (PCI_FUNC(pdev->devfn) == 1) in i5400_get_devices()
751 pvt->branchmap_werrors = pdev; in i5400_get_devices()
767 pci_dev_put(pvt->branchmap_werrors); in i5400_get_devices()
768 return -ENODEV; in i5400_get_devices()
772 if (PCI_FUNC(pdev->devfn) == 2) in i5400_get_devices()
775 pvt->fsb_error_regs = pdev; in i5400_get_devices()
777 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", in i5400_get_devices()
778 pci_name(pvt->system_address), in i5400_get_devices()
779 pvt->system_address->vendor, pvt->system_address->device); in i5400_get_devices()
780 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", in i5400_get_devices()
781 pci_name(pvt->branchmap_werrors), in i5400_get_devices()
782 pvt->branchmap_werrors->vendor, in i5400_get_devices()
783 pvt->branchmap_werrors->device); in i5400_get_devices()
784 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", in i5400_get_devices()
785 pci_name(pvt->fsb_error_regs), in i5400_get_devices()
786 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); in i5400_get_devices()
788 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, in i5400_get_devices()
790 if (!pvt->branch_0) { in i5400_get_devices()
796 pci_dev_put(pvt->fsb_error_regs); in i5400_get_devices()
797 pci_dev_put(pvt->branchmap_werrors); in i5400_get_devices()
798 return -ENODEV; in i5400_get_devices()
801 /* If this device claims to have more than 2 channels then in i5400_get_devices()
804 if (pvt->maxch < CHANNELS_PER_BRANCH) in i5400_get_devices()
807 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, in i5400_get_devices()
809 if (!pvt->branch_1) { in i5400_get_devices()
817 pci_dev_put(pvt->branch_0); in i5400_get_devices()
818 pci_dev_put(pvt->fsb_error_regs); in i5400_get_devices()
819 pci_dev_put(pvt->branchmap_werrors); in i5400_get_devices()
820 return -ENODEV; in i5400_get_devices()
845 amb_present = pvt->b0_ambpresent1; in determine_amb_present_reg()
847 amb_present = pvt->b0_ambpresent0; in determine_amb_present_reg()
850 amb_present = pvt->b1_ambpresent1; in determine_amb_present_reg()
852 amb_present = pvt->b1_ambpresent0; in determine_amb_present_reg()
868 /* There is one MTR for each slot pair of FB-DIMMs, in determine_mtr()
874 edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n", in determine_mtr()
880 mtr = pvt->b0_mtr[n]; in determine_mtr()
882 mtr = pvt->b1_mtr[n]; in determine_mtr()
909 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : in decode_mtr()
910 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : in decode_mtr()
911 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : in decode_mtr()
912 "65,536 - 16 rows"); in decode_mtr()
914 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : in decode_mtr()
915 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : in decode_mtr()
916 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : in decode_mtr()
944 addrBits -= 20; /* divide by 2^^20 */ in handle_channel()
945 addrBits -= 3; /* 8 bits per bytes */ in handle_channel()
947 dinfo->megabytes = 1 << addrBits; in handle_channel()
977 * Start with the highest dimm first, to display it first in calculate_dimm_size()
980 max_dimms = pvt->maxdimmperch; in calculate_dimm_size()
981 for (dimm = max_dimms - 1; dimm >= 0; dimm--) { in calculate_dimm_size()
986 n = snprintf(p, space, "---------------------------" in calculate_dimm_size()
987 "-------------------------------"); in calculate_dimm_size()
989 space -= n; in calculate_dimm_size()
996 space -= n; in calculate_dimm_size()
998 for (channel = 0; channel < pvt->maxch; channel++) { in calculate_dimm_size()
999 dinfo = &pvt->dimm_info[dimm][channel]; in calculate_dimm_size()
1001 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); in calculate_dimm_size()
1003 space -= n; in calculate_dimm_size()
1011 n = snprintf(p, space, "---------------------------" in calculate_dimm_size()
1012 "-------------------------------"); in calculate_dimm_size()
1014 space -= n; in calculate_dimm_size()
1022 space -= n; in calculate_dimm_size()
1023 for (channel = 0; channel < pvt->maxch; channel++) { in calculate_dimm_size()
1026 space -= n; in calculate_dimm_size()
1029 space -= n; in calculate_dimm_size()
1039 space -= n; in calculate_dimm_size()
1061 pvt = mci->pvt_info; in i5400_get_mc_regs()
1063 pci_read_config_dword(pvt->system_address, AMBASE, in i5400_get_mc_regs()
1064 &pvt->u.ambase_bottom); in i5400_get_mc_regs()
1065 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), in i5400_get_mc_regs()
1066 &pvt->u.ambase_top); in i5400_get_mc_regs()
1068 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", in i5400_get_mc_regs()
1069 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); in i5400_get_mc_regs()
1072 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); in i5400_get_mc_regs()
1073 pvt->tolm >>= 12; in i5400_get_mc_regs()
1075 pvt->tolm, pvt->tolm); in i5400_get_mc_regs()
1077 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); in i5400_get_mc_regs()
1079 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); in i5400_get_mc_regs()
1081 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); in i5400_get_mc_regs()
1082 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); in i5400_get_mc_regs()
1084 /* Get the MIR[0-1] regs */ in i5400_get_mc_regs()
1085 limit = (pvt->mir0 >> 4) & 0x0fff; in i5400_get_mc_regs()
1086 way0 = pvt->mir0 & 0x1; in i5400_get_mc_regs()
1087 way1 = pvt->mir0 & 0x2; in i5400_get_mc_regs()
1090 limit = (pvt->mir1 >> 4) & 0xfff; in i5400_get_mc_regs()
1091 way0 = pvt->mir1 & 0x1; in i5400_get_mc_regs()
1092 way1 = pvt->mir1 & 0x2; in i5400_get_mc_regs()
1096 /* Get the set of MTR[0-3] regs by each branch */ in i5400_get_mc_regs()
1101 pci_read_config_word(pvt->branch_0, where, in i5400_get_mc_regs()
1102 &pvt->b0_mtr[slot_row]); in i5400_get_mc_regs()
1105 slot_row, where, pvt->b0_mtr[slot_row]); in i5400_get_mc_regs()
1107 if (pvt->maxch < CHANNELS_PER_BRANCH) { in i5400_get_mc_regs()
1108 pvt->b1_mtr[slot_row] = 0; in i5400_get_mc_regs()
1113 pci_read_config_word(pvt->branch_1, where, in i5400_get_mc_regs()
1114 &pvt->b1_mtr[slot_row]); in i5400_get_mc_regs()
1116 slot_row, where, pvt->b1_mtr[slot_row]); in i5400_get_mc_regs()
1123 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); in i5400_get_mc_regs()
1125 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, in i5400_get_mc_regs()
1126 &pvt->b0_ambpresent0); in i5400_get_mc_regs()
1127 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); in i5400_get_mc_regs()
1128 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, in i5400_get_mc_regs()
1129 &pvt->b0_ambpresent1); in i5400_get_mc_regs()
1130 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); in i5400_get_mc_regs()
1133 if (pvt->maxch < CHANNELS_PER_BRANCH) { in i5400_get_mc_regs()
1134 pvt->b1_ambpresent0 = 0; in i5400_get_mc_regs()
1135 pvt->b1_ambpresent1 = 0; in i5400_get_mc_regs()
1140 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); in i5400_get_mc_regs()
1142 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, in i5400_get_mc_regs()
1143 &pvt->b1_ambpresent0); in i5400_get_mc_regs()
1144 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n", in i5400_get_mc_regs()
1145 pvt->b1_ambpresent0); in i5400_get_mc_regs()
1146 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, in i5400_get_mc_regs()
1147 &pvt->b1_ambpresent1); in i5400_get_mc_regs()
1148 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n", in i5400_get_mc_regs()
1149 pvt->b1_ambpresent1); in i5400_get_mc_regs()
1175 pvt = mci->pvt_info; in i5400_init_dimms()
1180 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 in i5400_init_dimms()
1183 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; in i5400_init_dimms()
1185 for (slot = 0; slot < mci->layers[2].size; slot++) { in i5400_init_dimms()
1194 size_mb = pvt->dimm_info[slot][channel].megabytes; in i5400_init_dimms()
1200 dimm->nr_pages = size_mb << 8; in i5400_init_dimms()
1201 dimm->grain = 8; in i5400_init_dimms()
1202 dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ? in i5400_init_dimms()
1204 dimm->mtype = MEM_FB_DDR2; in i5400_init_dimms()
1207 * is similar to Chipkill. in i5400_init_dimms()
1209 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ? in i5400_init_dimms()
1217 * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. in i5400_init_dimms()
1220 mci->dimms[0]->edac_mode = EDAC_SECDED; in i5400_init_dimms()
1234 pvt = mci->pvt_info; in i5400_enable_error_reporting()
1237 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, in i5400_enable_error_reporting()
1243 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, in i5400_enable_error_reporting()
1248 * i5400_probe1 Probe for ONE instance of device to see if it is
1261 return -EINVAL; in i5400_probe1()
1264 pdev->bus->number, in i5400_probe1()
1265 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); in i5400_probe1()
1268 if (PCI_FUNC(pdev->devfn) != 0) in i5400_probe1()
1269 return -ENODEV; in i5400_probe1()
1287 return -ENOMEM; in i5400_probe1()
1291 mci->pdev = &pdev->dev; /* record ptr to the generic device */ in i5400_probe1()
1293 pvt = mci->pvt_info; in i5400_probe1()
1294 pvt->system_address = pdev; /* Record this device in our private */ in i5400_probe1()
1295 pvt->maxch = MAX_CHANNELS; in i5400_probe1()
1296 pvt->maxdimmperch = DIMMS_PER_CHANNEL; in i5400_probe1()
1298 /* 'get' the pci devices we want to reserve for our use */ in i5400_probe1()
1302 /* Time to get serious */ in i5400_probe1()
1305 mci->mc_idx = 0; in i5400_probe1()
1306 mci->mtype_cap = MEM_FLAG_FB_DDR2; in i5400_probe1()
1307 mci->edac_ctl_cap = EDAC_FLAG_NONE; in i5400_probe1()
1308 mci->edac_cap = EDAC_FLAG_NONE; in i5400_probe1()
1309 mci->mod_name = "i5400_edac.c"; in i5400_probe1()
1310 mci->ctl_name = i5400_devs[dev_idx].ctl_name; in i5400_probe1()
1311 mci->dev_name = pci_name(pdev); in i5400_probe1()
1312 mci->ctl_page_to_phys = NULL; in i5400_probe1()
1314 /* Set the function pointer to an actual operation function */ in i5400_probe1()
1315 mci->edac_check = i5400_check_error; in i5400_probe1()
1320 …edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonze… in i5400_probe1()
1321 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ in i5400_probe1()
1327 /* add this new MC control structure to EDAC's list of MCs */ in i5400_probe1()
1339 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); in i5400_probe1()
1342 "%s(): Unable to create PCI control\n", in i5400_probe1()
1358 return -ENODEV; in i5400_probe1()
1380 return i5400_probe1(pdev, id->driver_data); in i5400_init_one()
1396 mci = edac_mc_del_mc(&pdev->dev); in i5400_remove_one()
1400 /* retrieve references to resources, and free those resources */ in i5400_remove_one()
1433 * Try to initialize this module for its devices
1466 MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "