drivers/edac/amd64_edac.h

324 struct amd64_pvt {  struct
325 	struct low_ops *ops;
328 	struct pci_dev *F1, *F2, *F3;
330 	u16 mc_node_id;		/* MC index of this MC node */
331 	u8 fam;			/* CPU family */
332 	u8 model;		/* ... model */
333 	u8 stepping;		/* ... stepping */
335 	int ext_model;		/* extended model value of this node */
338 	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
339 	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
340 	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
341 	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
342 	u32 nbcap;		/* North Bridge Capabilities */
343 	u32 nbcfg;		/* F10 North Bridge Configuration */
344 	u32 dhar;		/* DRAM Hoist reg */
345 	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
346 	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */
349 	struct chip_select csels[NUM_CONTROLLERS];
352 	struct dram_range ranges[DRAM_RANGES];
354 	u64 top_mem;		/* top of memory below 4GB */
355 	u64 top_mem2;		/* top of memory above 4GB */
357 	u32 dct_sel_lo;		/* DRAM Controller Select Low */
358 	u32 dct_sel_hi;		/* DRAM Controller Select High */
359 	u32 online_spare;	/* On-Line spare Reg */
360 	u32 gpu_umc_base;	/* Base address used for channel selection on GPUs */
363 	u8 ecc_sym_sz;
365 	const char *ctl_name;
366 	u16 f1_id, f2_id;
368 	u8 max_mcs;
370 	struct amd64_family_flags flags;
372 	struct error_injection injection;
380 	enum mem_type dram_type;
382 	struct amd64_umc *umc;	/* UMC registers */