Lines Matching +full:memory +full:- +full:controller

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
19 	  memory errors, cache errors, PCI errors, thermal throttling, etc..
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
60 	  Not all machines support hardware-driven error report. Some of those
61 	  provide a BIOS-driven error report mechanism via ACPI, using the
65 	  When this option is enabled, it will disable the hardware-driven
69 	  It should be noticed that keeping both GHES and a hardware-driven
82 	  memory scrubbers in the system. The common sysfs scrub interface
90 	  The EDAC ECS feature is optional and is designed to control on-die
97 	bool "EDAC memory repair feature"
99 	  The EDAC memory repair feature is optional and is designed to control
100 	  the memory devices with repair features, such as Post Package Repair
101 	  (PPR), memory sparing etc. The common sysfs memory repair interface
102 	  abstracts the control of various memory repair functionalities into
104 	  Say 'y/n' to enable/disable EDAC memory repair feature.
113 	  the AMD64 families (>= K8) of memory controllers.
118 	  AMD CPUs up to and excluding family 0x17 provide for Memory
123 	  When enabled, in each of the respective memory controller directories
126 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
127 	  - inject_word (0..8, 16-bit word of 16-byte section),
128 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
134 	tristate "Amazon's Annapurna Lab Memory Controller"
167 	  82443BX/GX memory controllers (440BX/GX chipsets).
202 	  E3-1200 based DRAM controllers.
223 	  i7 Core (Nehalem) Integrated Memory Controller that exists on
264 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
268 	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
278 	  Skylake server Integrated Memory Controllers. If your
279 	  system has non-volatile DIMMs you should also manually
290 	  10nm server Integrated Memory Controllers. If your
291 	  system has non-volatile DIMMs you should also manually
300 	  Pondicherry2 Integrated Memory Controller. This SoC IP is
302 	  micro-server but may appear on others in the future.
310 	  client SoC Integrated Memory Controller using In-Band ECC IP.
311 	  This In-Band ECC is first used on the Elkhart Lake SoC but
325 	  Support for error detection and correction on Freescale memory
336 	tristate "IBM CPC925 Memory Controller (PPC970FX)"
340 	  IBM CPC925 Bridge and Memory Controller, which is
345 	tristate "Highbank Memory Controller"
349 	  Calxeda Highbank memory controller.
356 	  Calxeda Highbank memory controller.
373 	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
380 	tristate "Cavium Octeon PCI Controller"
392 	  Cavium ThunderX memory controllers (LMC), Cache
409 	  Altera SDRAM Memory for Altera SoCs. Note that the
418 	  Altera L2 cache Memory for Altera SoCs. This option
422 	bool "Altera On-Chip RAM ECC"
426 	  Altera On-Chip RAM Memory for Altera SoCs.
433 	  Altera Ethernet FIFO Memory for Altera SoCs.
440 	  Altera NAND FIFO Memory for Altera SoCs.
447 	  Altera DMA FIFO Memory for Altera SoCs.
454 	  Altera USB FIFO Memory for Altera SoCs.
461 	  Altera QSPI FIFO Memory for Altera SoCs.
468 	  Altera SDMMC FIFO Memory for Altera SoCs.
484 	tristate "Synopsys DDR Memory Controller"
488 	  memory controller.
491 	tristate "APM X-Gene SoC"
495 	  APM X-Gene family of SOCs.
498 	tristate "Texas Instruments DDR3 ECC Controller"
504 	tristate "QCOM EDAC Controller"
511 	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
527 	tristate "Mellanox BlueField Memory ECC"
534 	tristate "ARM DMC-520 ECC"
538 	  SoCs with ARM DMC-520 DRAM controller.
541 	tristate "Xilinx ZynqMP OCM Controller"
545 	  Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
549 	tristate "Nuvoton NPCM DDR Memory Controller"
553 	  memory controller.
555 	  The memory controller supports single bit error correction, double bit
556 	  error detection (in-line ECC in which a section 1/8th of the memory
560 	tristate "Xilinx Versal DDR Memory Controller"
564 	  memory controller.
571 	tristate "Loongson Memory Controller"
575 	  family memory controller. This driver reports single bit
576 	  errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000