Lines Matching +full:has +full:- +full:ecc
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
53 has been initialized.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
90 The EDAC ECS feature is optional and is designed to control on-die
112 Support for error detection and correction of DRAM ECC errors on
119 Error Injection into the ECC detection circuits. The amd64_edac
126 - inject_section (0..3, 16-byte section of 64-byte cacheline),
127 - inject_word (0..8, 16-bit word of 16-byte section),
128 - inject_ecc_vector (hex ecc vector: select bits of inject word)
131 which trigger the DRAM ECC Read and Write respectively.
202 E3-1200 based DRAM controllers.
264 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
279 system has non-volatile DIMMs you should also manually
291 system has non-volatile DIMMs you should also manually
302 micro-server but may appear on others in the future.
310 client SoC Integrated Memory Controller using In-Band ECC IP.
311 This In-Band ECC is first used on the Elkhart Lake SoC but
397 bool "Altera SOCFPGA ECC"
405 bool "Altera SDRAM ECC"
414 bool "Altera L2 Cache ECC"
422 bool "Altera On-Chip RAM ECC"
426 Altera On-Chip RAM Memory for Altera SoCs.
429 bool "Altera Ethernet FIFO ECC"
436 bool "Altera NAND FIFO ECC"
443 bool "Altera DMA FIFO ECC"
450 bool "Altera USB FIFO ECC"
457 bool "Altera QSPI FIFO ECC"
464 bool "Altera SDMMC FIFO ECC"
477 bool "Marvell Armada XP DDR and L2 Cache ECC"
491 tristate "APM X-Gene SoC"
495 APM X-Gene family of SOCs.
498 tristate "Texas Instruments DDR3 ECC Controller"
523 First, ECC must be configured in the bootloader. Then, this driver
527 tristate "Mellanox BlueField Memory ECC"
534 tristate "ARM DMC-520 ECC"
538 SoCs with ARM DMC-520 DRAM controller.
556 error detection (in-line ECC in which a section 1/8th of the memory
557 device used to store data is used for ECC storage).
576 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000