Kconfig - OpenGrok cross reference for /linux-6.15/drivers/edac/Kconfig

13 	tristate "EDAC (Error Detection And Correction) reporting"
16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
60 	  Not all machines support hardware-driven error report. Some of those
61 	  provide a BIOS-driven error report mechanism via ACPI, using the
62 	  APEI/GHES driver. By enabling this option, the error reports provided
65 	  When this option is enabled, it will disable the hardware-driven
69 	  It should be noticed that keeping both GHES and a hardware-driven
70 	  error mechanism won't work well, as BIOS will race with OS, while
71 	  reading the error registers. So, if you want to not use "Firmware
72 	  first" GHES error mechanism, you should disable GHES either at
88 	bool "EDAC ECS (Error Check Scrub) feature"
90 	  The EDAC ECS feature is optional and is designed to control on-die
91 	  error check scrub (e.g., DDR5 ECS) in the system. The common sysfs
112 	  Support for error detection and correction of DRAM ECC errors on
115 	  When EDAC_DEBUG is enabled, hardware error injection facilities
119 	  Error Injection into the ECC detection circuits. The amd64_edac
126 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
127 	  - inject_word (0..8, 16-bit word of 16-byte section),
128 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
137 	  Support for error detection and correction for Amazon's Annapurna
138 	  Labs Alpine chips which allow 1 bit correction and 2 bits detection.
144 	  Support for error detection and correction on the AMD 76x
151 	  Support for error detection and correction on the Intel
158 	  Support for error detection and correction on the Intel
166 	  Support for error detection and correction on the Intel
173 	  Support for error detection and correction on the Intel
180 	  Support for error detection and correction on the Intel
187 	  Support for error detection and correction on the Intel
194 	  Support for error detection and correction on the Intel
201 	  Support for error detection and correction on the Intel
202 	  E3-1200 based DRAM controllers.
208 	  Support for error detection and correction on the Intel
215 	  Support for error detection and correction the Intel
222 	  Support for error detection and correction the Intel
231 	  Support for error detection and correction on the Intel
238 	  Support for error detection and correction on the Radisys
246 	  Support for error detection and correction the Intel
253 	  Support for error detection and correction the Intel
260 	  Support for error detection and correction the Intel
264 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
267 	  Support for error detection and correction the Intel
277 	  Support for error detection and correction the Intel
279 	  system has non-volatile DIMMs you should also manually
289 	  Support for error detection and correction the Intel
291 	  system has non-volatile DIMMs you should also manually
299 	  Support for error detection and correction on the Intel
302 	  micro-server but may appear on others in the future.
309 	  Support for error detection and correction on the Intel
310 	  client SoC Integrated Memory Controller using In-Band ECC IP.
311 	  This In-Band ECC is first used on the Elkhart Lake SoC but
318 	  Support for error detection and correction on the Freescale
325 	  Support for error detection and correction on Freescale memory
332 	  Support for error detection and correction on PA Semi
339 	  Support for error detection and correction on the
348 	  Support for error detection and correction on the
355 	  Support for error detection and correction on the
362 	  Support for error detection and correction on the primary caches of
369 	  Support for error detection and correction on the
376 	  Support for error detection and correction on the
383 	  Support for error detection and correction on the
391 	  Support for error detection and correction on the
400 	  Support for error detection and correction on the
408 	  Support for error detection and correction on the
417 	  Support for error detection and correction on the
422 	bool "Altera On-Chip RAM ECC"
425 	  Support for error detection and correction on the
426 	  Altera On-Chip RAM Memory for Altera SoCs.
432 	  Support for error detection and correction on the
439 	  Support for error detection and correction on the
446 	  Support for error detection and correction on the
453 	  Support for error detection and correction on the
460 	  Support for error detection and correction on the
467 	  Support for error detection and correction on the
474 	  Support for error detection and correction on the SiFive SoCs.
480 	  Support for error correction and detection on the Marvell Aramada XP
487 	  Support for error detection and correction on the Synopsys DDR
491 	tristate "APM X-Gene SoC"
494 	  Support for error detection and correction on the
495 	  APM X-Gene family of SOCs.
501 	  Support for error detection and correction on the TI SoCs.
507 	  Support for error detection and correction on the
511 	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
521 	  Support for error detection and correction on the Aspeed AST BMC SoC.
524 	  will expose error counters via the EDAC kernel framework.
530 	  Support for error detection and correction on the
534 	tristate "ARM DMC-520 ECC"
537 	  Support for error detection and correction on the
538 	  SoCs with ARM DMC-520 DRAM controller.
544 	  This driver supports error detection and correction for the
552 	  Support for error detection and correction on the Nuvoton NPCM DDR
555 	  The memory controller supports single bit error correction, double bit
556 	  error detection (in-line ECC in which a section 1/8th of the memory
563 	  Support for error detection and correction on the Xilinx Versal DDR
574 	  Support for error detection and correction on the Loongson
576 	  errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000