Lines Matching +full:ddr +full:- +full:config
6 config EDAC_ATOMIC_SCRUB
9 config EDAC_SUPPORT
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
34 config EDAC_DEBUG
40 levels are 0-4 (from low to high) and by default it is set to 2.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
55 config EDAC_GHES
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
78 config EDAC_SCRUB
87 config EDAC_ECS
90 The EDAC ECS feature is optional and is designed to control on-die
96 config EDAC_MEM_REPAIR
106 config EDAC_AMD64
126 - inject_section (0..3, 16-byte section of 64-byte cacheline),
127 - inject_word (0..8, 16-bit word of 16-byte section),
128 - inject_ecc_vector (hex ecc vector: select bits of inject word)
133 config EDAC_AL_MC
140 config EDAC_AMD76X
147 config EDAC_E7XXX
154 config EDAC_E752X
161 config EDAC_I82443BXGX
169 config EDAC_I82875P
176 config EDAC_I82975X
183 config EDAC_I3000
190 config EDAC_I3200
197 config EDAC_IE31200
202 E3-1200 based DRAM controllers.
204 config EDAC_X38
211 config EDAC_I5400
218 config EDAC_I7CORE
227 config EDAC_I82860
234 config EDAC_R82600
241 config EDAC_I5000
249 config EDAC_I5100
256 config EDAC_I7300
263 config EDAC_SBRIDGE
264 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
270 config EDAC_SKX
279 system has non-volatile DIMMs you should also manually
282 config EDAC_I10NM
291 system has non-volatile DIMMs you should also manually
294 config EDAC_PND2
302 micro-server but may appear on others in the future.
304 config EDAC_IGEN6
310 client SoC Integrated Memory Controller using In-Band ECC IP.
311 This In-Band ECC is first used on the Elkhart Lake SoC but
314 config EDAC_MPC85XX
321 config EDAC_LAYERSCAPE
322 tristate "Freescale Layerscape DDR"
328 config EDAC_PASEMI
335 config EDAC_CPC925
344 config EDAC_HIGHBANK_MC
351 config EDAC_HIGHBANK_L2
358 config EDAC_OCTEON_PC
365 config EDAC_OCTEON_L2C
372 config EDAC_OCTEON_LMC
379 config EDAC_OCTEON_PCI
386 config EDAC_THUNDERX
396 config EDAC_ALTERA
404 config EDAC_ALTERA_SDRAM
413 config EDAC_ALTERA_L2C
421 config EDAC_ALTERA_OCRAM
422 bool "Altera On-Chip RAM ECC"
426 Altera On-Chip RAM Memory for Altera SoCs.
428 config EDAC_ALTERA_ETHERNET
435 config EDAC_ALTERA_NAND
442 config EDAC_ALTERA_DMA
449 config EDAC_ALTERA_USB
456 config EDAC_ALTERA_QSPI
463 config EDAC_ALTERA_SDMMC
470 config EDAC_SIFIVE
476 config EDAC_ARMADA_XP
477 bool "Marvell Armada XP DDR and L2 Cache ECC"
481 DDR RAM and L2 cache controllers.
483 config EDAC_SYNOPSYS
484 tristate "Synopsys DDR Memory Controller"
487 Support for error detection and correction on the Synopsys DDR
490 config EDAC_XGENE
491 tristate "APM X-Gene SoC"
495 APM X-Gene family of SOCs.
497 config EDAC_TI
503 config EDAC_QCOM
517 config EDAC_ASPEED
526 config EDAC_BLUEFIELD
533 config EDAC_DMC520
534 tristate "ARM DMC-520 ECC"
538 SoCs with ARM DMC-520 DRAM controller.
540 config EDAC_ZYNQMP
548 config EDAC_NPCM
549 tristate "Nuvoton NPCM DDR Memory Controller"
552 Support for error detection and correction on the Nuvoton NPCM DDR
556 error detection (in-line ECC in which a section 1/8th of the memory
559 config EDAC_VERSAL
560 tristate "Xilinx Versal DDR Memory Controller"
563 Support for error detection and correction on the Xilinx Versal DDR
570 config EDAC_LOONGSON
576 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000