Lines Matching +full:y +full:- +full:rp
1 // SPDX-License-Identifier: GPL-2.0-only
55 struct acpi_cdat_header *hdr = &header->cdat; in cdat_dsmas_handler()
63 len = le16_to_cpu((__force __le16)hdr->length); in cdat_dsmas_handler()
66 return -EINVAL; in cdat_dsmas_handler()
74 return -ENOMEM; in cdat_dsmas_handler()
76 dent->handle = dsmas->dsmad_handle; in cdat_dsmas_handler()
77 dent->dpa_range.start = le64_to_cpu((__force __le64)dsmas->dpa_base_address); in cdat_dsmas_handler()
78 dent->dpa_range.end = le64_to_cpu((__force __le64)dsmas->dpa_base_address) + in cdat_dsmas_handler()
79 le64_to_cpu((__force __le64)dsmas->dpa_length) - 1; in cdat_dsmas_handler()
81 rc = xa_insert(dsmas_xa, dent->handle, dent, GFP_KERNEL); in cdat_dsmas_handler()
95 coord->read_latency = val; in __cxl_access_coordinate_set()
96 coord->write_latency = val; in __cxl_access_coordinate_set()
99 coord->read_latency = val; in __cxl_access_coordinate_set()
102 coord->write_latency = val; in __cxl_access_coordinate_set()
105 coord->read_bandwidth = val; in __cxl_access_coordinate_set()
106 coord->write_bandwidth = val; in __cxl_access_coordinate_set()
109 coord->read_bandwidth = val; in __cxl_access_coordinate_set()
112 coord->write_bandwidth = val; in __cxl_access_coordinate_set()
127 struct acpi_cdat_header *hdr = &header->cdat; in cdat_dslbis_handler()
137 len = le16_to_cpu((__force __le16)hdr->length); in cdat_dslbis_handler()
140 return -EINVAL; in cdat_dslbis_handler()
147 if (dslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH) in cdat_dslbis_handler()
151 if ((dslbis->flags & ACPI_HMAT_MEMORY_HIERARCHY) != ACPI_HMAT_MEMORY) in cdat_dslbis_handler()
154 dent = xa_load(dsmas_xa, dslbis->handle); in cdat_dslbis_handler()
160 le_base = (__force __le64)dslbis->entry_base_unit; in cdat_dslbis_handler()
161 le_val = (__force __le16)dslbis->entry[0]; in cdat_dslbis_handler()
163 dslbis->data_type); in cdat_dslbis_handler()
165 cxl_access_coordinate_set(dent->cdat_coord, dslbis->data_type, val); in cdat_dslbis_handler()
175 return -ENOENT; in cdat_table_parse_output()
186 dsmas_xa, port->cdat.table, port->cdat.length); in cxl_cdat_endpoint_process()
192 dsmas_xa, port->cdat.table, port->cdat.length); in cxl_cdat_endpoint_process()
207 dev_dbg(&port->dev, "Failed to retrieve ep perf coordinates.\n"); in cxl_port_perf_data_calculate()
214 return -ENODEV; in cxl_port_perf_data_calculate()
216 if (!cxl_root->ops || !cxl_root->ops->qos_class) in cxl_port_perf_data_calculate()
217 return -EOPNOTSUPP; in cxl_port_perf_data_calculate()
222 cxl_coordinates_combine(dent->coord, dent->cdat_coord, ep_c); in cxl_port_perf_data_calculate()
223 dent->entries = 1; in cxl_port_perf_data_calculate()
224 rc = cxl_root->ops->qos_class(cxl_root, in cxl_port_perf_data_calculate()
225 &dent->coord[ACCESS_COORDINATE_CPU], in cxl_port_perf_data_calculate()
231 dent->qos_class = qos_class; in cxl_port_perf_data_calculate()
235 return -ENOENT; in cxl_port_perf_data_calculate()
244 dpa_perf->coord[i] = dent->coord[i]; in update_perf_entry()
245 dpa_perf->cdat_coord[i] = dent->cdat_coord[i]; in update_perf_entry()
247 dpa_perf->dpa_range = dent->dpa_range; in update_perf_entry()
248 dpa_perf->qos_class = dent->qos_class; in update_perf_entry()
251 &dent->dpa_range, dpa_perf->qos_class, in update_perf_entry()
252 dent->coord[ACCESS_COORDINATE_CPU].read_bandwidth, in update_perf_entry()
253 dent->coord[ACCESS_COORDINATE_CPU].write_bandwidth, in update_perf_entry()
254 dent->coord[ACCESS_COORDINATE_CPU].read_latency, in update_perf_entry()
255 dent->coord[ACCESS_COORDINATE_CPU].write_latency); in update_perf_entry()
261 struct device *dev = cxlds->dev; in cxl_memdev_set_qos_class()
268 for (int i = 0; i < cxlds->nr_partitions; i++) { in cxl_memdev_set_qos_class()
269 struct resource *res = &cxlds->part[i].res; in cxl_memdev_set_qos_class()
271 .start = res->start, in cxl_memdev_set_qos_class()
272 .end = res->end, in cxl_memdev_set_qos_class()
275 if (range_contains(&range, &dent->dpa_range)) { in cxl_memdev_set_qos_class()
277 &cxlds->part[i].perf); in cxl_memdev_set_qos_class()
285 &dent->dpa_range); in cxl_memdev_set_qos_class()
298 if (cxlrd->qos_class == CXL_QOS_CLASS_INVALID) in match_cxlrd_qos_class()
301 if (cxlrd->qos_class == dev_qos_class) in match_cxlrd_qos_class()
317 if (dpa_perf->qos_class == CXL_QOS_CLASS_INVALID) in cxl_qos_match()
320 if (!device_for_each_child(&root_port->dev, &dpa_perf->qos_class, in cxl_qos_match()
337 cxlsd = &cxlrd->cxlsd; in match_cxlrd_hb()
340 for (int i = 0; i < cxlsd->nr_targets; i++) { in match_cxlrd_hb()
341 if (host_bridge == cxlsd->target[i]->dport_dev) in match_cxlrd_hb()
350 struct cxl_dev_state *cxlds = cxlmd->cxlds; in cxl_qos_class_verify()
354 find_cxl_root(cxlmd->endpoint); in cxl_qos_class_verify()
363 root_port = &cxl_root->port; in cxl_qos_class_verify()
371 if (!device_for_each_child(&root_port->dev, in cxl_qos_class_verify()
372 cxlmd->endpoint->host_bridge, in cxl_qos_class_verify()
374 for (int i = 0; i < cxlds->nr_partitions; i++) { in cxl_qos_class_verify()
375 struct cxl_dpa_perf *perf = &cxlds->part[i].perf; in cxl_qos_class_verify()
382 for (int i = 0; i < cxlds->nr_partitions; i++) { in cxl_qos_class_verify()
383 struct cxl_dpa_perf *perf = &cxlds->part[i].perf; in cxl_qos_class_verify()
405 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); in DEFINE_FREE()
406 struct cxl_dev_state *cxlds = cxlmd->cxlds; in DEFINE_FREE()
412 if (!port->cdat.table) in DEFINE_FREE()
417 dev_dbg(&port->dev, "Failed to parse CDAT: %d\n", rc); in DEFINE_FREE()
423 dev_dbg(&port->dev, "Failed to do perf coord calculations.\n"); in DEFINE_FREE()
441 int size = sizeof(header->cdat) + sizeof(tbl->sslbis_header); in cdat_sslbis_handler()
444 struct device *dev = &port->dev; in cdat_sslbis_handler()
448 len = le16_to_cpu((__force __le16)header->cdat.length); in cdat_sslbis_handler()
449 remain = len - size; in cdat_sslbis_handler()
450 if (!remain || remain % sizeof(tbl->entries[0]) || in cdat_sslbis_handler()
453 return -EINVAL; in cdat_sslbis_handler()
456 sslbis = &tbl->sslbis_header; in cdat_sslbis_handler()
458 if (sslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH) in cdat_sslbis_handler()
461 entries = remain / sizeof(tbl->entries[0]); in cdat_sslbis_handler()
463 return -EINVAL; in cdat_sslbis_handler()
466 u16 x = le16_to_cpu((__force __le16)tbl->entries[i].portx_id); in cdat_sslbis_handler()
467 u16 y = le16_to_cpu((__force __le16)tbl->entries[i].porty_id); in cdat_sslbis_handler() local
477 dsp_id = y; in cdat_sslbis_handler()
480 switch (y) { in cdat_sslbis_handler()
488 dsp_id = y; in cdat_sslbis_handler()
497 le_base = (__force __le64)tbl->sslbis_header.entry_base_unit; in cdat_sslbis_handler()
498 le_val = (__force __le16)tbl->entries[i].latency_or_bandwidth; in cdat_sslbis_handler()
500 sslbis->data_type); in cdat_sslbis_handler()
502 xa_for_each(&port->dports, index, dport) { in cdat_sslbis_handler()
504 dsp_id == dport->port_id) { in cdat_sslbis_handler()
505 cxl_access_coordinate_set(dport->coord, in cdat_sslbis_handler()
506 sslbis->data_type, in cdat_sslbis_handler()
519 if (!port->cdat.table) in cxl_switch_parse_cdat()
523 port, port->cdat.table, port->cdat.length); in cxl_switch_parse_cdat()
526 dev_dbg(&port->dev, "Failed to parse SSLBIS: %d\n", rc); in cxl_switch_parse_cdat()
534 if (c1->write_bandwidth && c2->write_bandwidth) in __cxl_coordinates_combine()
535 out->write_bandwidth = min(c1->write_bandwidth, in __cxl_coordinates_combine()
536 c2->write_bandwidth); in __cxl_coordinates_combine()
537 out->write_latency = c1->write_latency + c2->write_latency; in __cxl_coordinates_combine()
539 if (c1->read_bandwidth && c2->read_bandwidth) in __cxl_coordinates_combine()
540 out->read_bandwidth = min(c1->read_bandwidth, in __cxl_coordinates_combine()
541 c2->read_bandwidth); in __cxl_coordinates_combine()
542 out->read_latency = c1->read_latency + c2->read_latency; in __cxl_coordinates_combine()
546 * cxl_coordinates_combine - Combine the two input coordinates
578 .start = dpa_res->start, in dpa_perf_contains()
579 .end = dpa_res->end, in dpa_perf_contains()
582 return range_contains(&perf->dpa_range, &dpa); in dpa_perf_contains()
588 struct cxl_dev_state *cxlds = cxlmd->cxlds; in cxled_get_dpa_perf()
591 if (cxled->part < 0) in cxled_get_dpa_perf()
592 return ERR_PTR(-EINVAL); in cxled_get_dpa_perf()
593 perf = &cxlds->part[cxled->part].perf; in cxled_get_dpa_perf()
596 return ERR_PTR(-EINVAL); in cxled_get_dpa_perf()
598 if (!dpa_perf_contains(perf, cxled->dpa_res)) in cxled_get_dpa_perf()
599 return ERR_PTR(-EINVAL); in cxled_get_dpa_perf()
614 * cxl_endpoint_gather_bandwidth - collect all the endpoint bandwidth in an xarray
621 * Return: 0 for success or -errno
624 * an xarray indexed by the upstream device of the switch or the RP
629 * device is directly connected to a RP, then no SSLBIS is involved.
636 struct cxl_port *endpoint = to_cxl_port(cxled->cxld.dev.parent); in cxl_endpoint_gather_bandwidth()
637 struct cxl_port *parent_port = to_cxl_port(endpoint->dev.parent); in cxl_endpoint_gather_bandwidth()
638 struct cxl_port *gp_port = to_cxl_port(parent_port->dev.parent); in cxl_endpoint_gather_bandwidth()
643 struct cxl_dev_state *cxlds = cxlmd->cxlds; in cxl_endpoint_gather_bandwidth()
644 struct pci_dev *pdev = to_pci_dev(cxlds->dev); in cxl_endpoint_gather_bandwidth()
651 if (!dev_is_pci(cxlds->dev)) in cxl_endpoint_gather_bandwidth()
652 return -ENODEV; in cxl_endpoint_gather_bandwidth()
654 if (cxlds->rcd) in cxl_endpoint_gather_bandwidth()
655 return -ENODEV; in cxl_endpoint_gather_bandwidth()
668 index = (unsigned long)endpoint->parent_dport->dport_dev; in cxl_endpoint_gather_bandwidth()
670 index = (unsigned long)parent_port->uport_dev; in cxl_endpoint_gather_bandwidth()
678 return -ENOMEM; in cxl_endpoint_gather_bandwidth()
683 perf_ctx->port = parent_port; in cxl_endpoint_gather_bandwidth()
695 cxl_coordinates_combine(ep_coord, pci_coord, perf->cdat_coord); in cxl_endpoint_gather_bandwidth()
719 * of the endpoints with the same switch upstream device or RP. in cxl_endpoint_gather_bandwidth()
721 cxl_bandwidth_add(perf_ctx->coord, perf_ctx->coord, ep_coord); in cxl_endpoint_gather_bandwidth()
742 * cxl_switch_gather_bandwidth - collect all the bandwidth at switch level in an xarray in DEFINE_FREE()
749 * or ERR_PTR(-errno) in DEFINE_FREE()
754 * device or a RP device. The function can be iterated over multiple switches in DEFINE_FREE()
772 return ERR_PTR(-ENOMEM); in DEFINE_FREE()
777 struct cxl_port *port = ctx->port; in DEFINE_FREE()
778 struct cxl_port *parent_port = to_cxl_port(port->dev.parent); in DEFINE_FREE()
779 struct cxl_port *gp_port = to_cxl_port(parent_port->dev.parent); in DEFINE_FREE()
780 struct cxl_dport *dport = port->parent_dport; in DEFINE_FREE()
794 us_index = (unsigned long)port->parent_dport->dport_dev; in DEFINE_FREE()
796 us_index = (unsigned long)parent_port->uport_dev; in DEFINE_FREE()
804 return ERR_PTR(-ENOMEM); in DEFINE_FREE()
810 us_ctx->port = parent_port; in DEFINE_FREE()
818 return ERR_PTR(-EINVAL); in DEFINE_FREE()
823 return ERR_PTR(-ENXIO); in DEFINE_FREE()
829 cxl_coordinates_combine(coords, coords, ctx->coord); in DEFINE_FREE()
836 cxl_coordinates_combine(coords, coords, dport->coord); in DEFINE_FREE()
842 cxl_bandwidth_add(us_ctx->coord, us_ctx->coord, coords); in DEFINE_FREE()
848 dev_dbg(&cxlr->dev, in DEFINE_FREE()
850 return ERR_PTR(-EOPNOTSUPP); in DEFINE_FREE()
859 * cxl_rp_gather_bandwidth - handle the root port level bandwidth collection
863 * Return: xarray that holds cxl_perf_ctx per host bridge or ERR_PTR(-errno)
873 return ERR_PTR(-ENOMEM); in cxl_rp_gather_bandwidth()
877 struct cxl_port *port = ctx->port; in cxl_rp_gather_bandwidth()
878 unsigned long hb_index = (unsigned long)port->uport_dev; in cxl_rp_gather_bandwidth()
888 return ERR_PTR(-ENOMEM); in cxl_rp_gather_bandwidth()
893 hb_ctx->port = port; in cxl_rp_gather_bandwidth()
896 cxl_bandwidth_add(hb_ctx->coord, hb_ctx->coord, ctx->coord); in cxl_rp_gather_bandwidth()
903 * cxl_hb_gather_bandwidth - handle the host bridge level bandwidth collection
907 * Return: xarray that holds cxl_perf_ctx per ACPI0017 device or ERR_PTR(-errno)
917 return ERR_PTR(-ENOMEM); in cxl_hb_gather_bandwidth()
921 struct cxl_port *port = ctx->port; in cxl_hb_gather_bandwidth()
928 parent_port = to_cxl_port(port->dev.parent); in cxl_hb_gather_bandwidth()
929 mw_index = (unsigned long)parent_port->uport_dev; in cxl_hb_gather_bandwidth()
937 return ERR_PTR(-ENOMEM); in cxl_hb_gather_bandwidth()
944 dport = port->parent_dport; in cxl_hb_gather_bandwidth()
945 cxl_coordinates_combine(ctx->coord, ctx->coord, dport->coord); in cxl_hb_gather_bandwidth()
946 cxl_bandwidth_add(mw_ctx->coord, mw_ctx->coord, ctx->coord); in cxl_hb_gather_bandwidth()
953 * cxl_region_update_bandwidth - Update the bandwidth access coordinates of a region
966 cxl_bandwidth_add(coord, coord, ctx->coord); in cxl_region_update_bandwidth()
969 cxlr->coord[i].read_bandwidth = coord[i].read_bandwidth; in cxl_region_update_bandwidth()
970 cxlr->coord[i].write_bandwidth = coord[i].write_bandwidth; in cxl_region_update_bandwidth()
975 * cxl_region_shared_upstream_bandwidth_update - Recalculate the bandwidth for
1001 for (int i = 0; i < cxlr->params.nr_targets; i++) { in cxl_region_shared_upstream_bandwidth_update()
1002 struct cxl_endpoint_decoder *cxled = cxlr->params.targets[i]; in cxl_region_shared_upstream_bandwidth_update()
1012 if (root_count && root_count != cxlr->params.nr_targets) { in cxl_region_shared_upstream_bandwidth_update()
1013 dev_dbg(&cxlr->dev, in cxl_region_shared_upstream_bandwidth_update()
1068 cxlr->coord[i].read_latency = max_t(unsigned int, in cxl_region_perf_data_calculate()
1069 cxlr->coord[i].read_latency, in cxl_region_perf_data_calculate()
1070 perf->coord[i].read_latency); in cxl_region_perf_data_calculate()
1071 cxlr->coord[i].write_latency = max_t(unsigned int, in cxl_region_perf_data_calculate()
1072 cxlr->coord[i].write_latency, in cxl_region_perf_data_calculate()
1073 perf->coord[i].write_latency); in cxl_region_perf_data_calculate()
1074 cxlr->coord[i].read_bandwidth += perf->coord[i].read_bandwidth; in cxl_region_perf_data_calculate()
1075 cxlr->coord[i].write_bandwidth += perf->coord[i].write_bandwidth; in cxl_region_perf_data_calculate()
1082 return hmat_update_target_coordinates(nid, &cxlr->coord[access], access); in cxl_update_hmat_access_coordinates()