Lines Matching +full:memory +full:- +full:to +full:- +full:memory

1 # SPDX-License-Identifier: GPL-2.0-only
14 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
15 locally, the CXL.mem protocol allows devices to be fully coherent
16 memory targets, the CXL.io protocol is equivalent to PCI Express.
17 Say 'y' to enable support for the configuration and management of
26 The CXL specification defines a "CXL memory device" sub-class in the
27 PCI "memory controller" base class of devices. Device's identified by
29 memory to be mapped into the system address map (Host-managed Device
30 Memory (HDM)).
32 Say 'y/m' to enable a driver that will attach to CXL memory expander
33 devices enumerated by the memory device class code for configuration
40 bool "RAW Command Interface for Memory Devices"
51 the driver it is useful to be able to submit any possible command to
52 the hardware, even commands that may crash the kernel due to their
53 potential impact to memory currently in use by the kernel.
66 Enable support for host managed device memory (HDM) resources
67 published by a platform's ACPI CXL memory layout description. See
69 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
70 (https://www.computeexpresslink.org/spec-landing). The CXL core
71 consumes these resource to publish the root of a cxl_port decode
72 hierarchy to map regions that represent System RAM, or Persistent
73 Memory regions to be managed by LIBNVDIMM.
78 tristate "CXL PMEM: Persistent Memory Support"
82 In addition to typical memory resources a platform may also advertise
83 support for persistent memory attached via CXL. This support is
84 managed via a bridge driver from CXL to the LIBNVDIMM system
85 subsystem. Say 'y/m' to enable support for enumerating and
86 provisioning the persistent memory capacity of CXL memory expanders.
91 tristate "CXL: Memory Expansion"
95 The CXL.mem protocol allows a device to act as a provider of "System
96 RAM" and/or "Persistent Memory" that is fully coherent as if the
97 memory were attached to the typical CPU memory controller. This is
98 known as HDM "Host-managed Device Memory".
100 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
101 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
112 optionally defined features such as memory sparing or post package
133 Enable the CXL core to enumerate and provision CXL regions. A CXL
135 system-physical address range. For CXL regions established by
136 platform-firmware this option enables memory error handling to
137 identify the devices participating in a given interleaved memory
138 range. Otherwise, platform-firmware managed CXL is enabled by being
148 the content of CPU caches without notifying those caches to
150 to invalidate caches when those events occur. If that invalidation
151 fails the region will fail to enable. Reasons for cache
152 invalidation failure are due to the CPU not providing a cache
153 invalidation mechanism. For example usage of wbinvd is restricted to