Lines Matching +full:0 +full:x100008
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
26 #define QM_IRQ_VECTOR_MASK GENMASK(15, 0)
27 #define QM_IRQ_TYPE_MASK GENMASK(15, 0)
29 #define QM_ABN_IRQ_TYPE_MASK GENMASK(7, 0)
32 #define QM_MB_PING_ALL_VFS 0xffff
36 #define QM_SQ_HOP_NUM_SHIFT 0
40 #define QM_SQ_PRIORITY_SHIFT 0
43 #define QM_QC_PASID_ENABLE 0x1
46 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
47 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc).w11) >> 6) & 0x1)
50 #define QM_CQ_HOP_NUM_SHIFT 0
54 #define QM_CQ_PHASE_SHIFT 0
57 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
59 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc).w11) >> 6) & 0x1)
65 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
66 #define QM_EQE_CQN_MASK GENMASK(15, 0)
68 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
70 #define QM_AEQE_TYPE_MASK 0xf
71 #define QM_AEQE_CQN_MASK GENMASK(15, 0)
72 #define QM_CQ_OVERFLOW 0
77 #define QM_XQ_DEPTH_MASK GENMASK(15, 0)
79 #define QM_DOORBELL_CMD_SQ 0
84 #define QM_DOORBELL_BASE_V1 0x340
88 #define QM_PAGE_SIZE 0x0034
89 #define QM_QP_DB_INTERVAL 0x10000
90 #define QM_DB_TIMEOUT_CFG 0x100074
91 #define QM_DB_TIMEOUT_SET 0x1fffff
93 #define QM_MEM_START_INIT 0x100040
94 #define QM_MEM_INIT_DONE 0x100044
95 #define QM_VFT_CFG_RDY 0x10006c
96 #define QM_VFT_CFG_OP_WR 0x100058
97 #define QM_VFT_CFG_TYPE 0x10005c
98 #define QM_VFT_CFG 0x100060
99 #define QM_VFT_CFG_OP_ENABLE 0x100054
100 #define QM_PM_CTRL 0x100148
103 #define QM_SUB_VERSION_ID 0x210
105 #define QM_VFT_CFG_DATA_L 0x100064
106 #define QM_VFT_CFG_DATA_H 0x100068
119 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
121 #define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)
124 #define QM_ABNORMAL_INT_SOURCE 0x100000
125 #define QM_ABNORMAL_INT_MASK 0x100004
126 #define QM_ABNORMAL_INT_MASK_VALUE 0x7fff
127 #define QM_ABNORMAL_INT_STATUS 0x100008
128 #define QM_ABNORMAL_INT_SET 0x10000c
129 #define QM_ABNORMAL_INF00 0x100010
130 #define QM_FIFO_OVERFLOW_TYPE 0xc0
132 #define QM_FIFO_OVERFLOW_VF 0x3f
134 #define QM_ABNORMAL_INF01 0x100014
135 #define QM_DB_TIMEOUT_TYPE 0xc0
137 #define QM_DB_TIMEOUT_VF 0x3f
139 #define QM_ABNORMAL_INF02 0x100018
141 #define QM_RAS_CE_ENABLE 0x1000ec
142 #define QM_RAS_FE_ENABLE 0x1000f0
143 #define QM_RAS_NFE_ENABLE 0x1000f4
144 #define QM_RAS_CE_THRESHOLD 0x1000f8
146 #define QM_OOO_SHUTDOWN_SEL 0x1040f8
147 #define QM_AXI_RRESP_ERR BIT(0)
153 #define QM_PEH_VENDOR_ID 0x1000d8
154 #define ACC_VENDOR_ID_VALUE 0x5a5a
155 #define QM_PEH_DFX_INFO0 0x1000fc
156 #define QM_PEH_DFX_INFO1 0x100100
157 #define QM_PEH_DFX_MASK (BIT(0) | BIT(2))
160 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
161 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
163 #define ACC_MASTER_TRANS_RETURN 0x300150
164 #define ACC_MASTER_GLOBAL_CTRL 0x300000
165 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
167 #define ACC_AM_ROB_ECC_INT_STS 0x300104
172 #define QM_IFC_READY_STATUS 0x100128
173 #define QM_IFC_INT_SET_P 0x100130
174 #define QM_IFC_INT_CFG 0x100134
175 #define QM_IFC_INT_SOURCE_P 0x100138
176 #define QM_IFC_INT_SOURCE_V 0x0020
177 #define QM_IFC_INT_MASK 0x0024
178 #define QM_IFC_INT_STATUS 0x0028
179 #define QM_IFC_INT_SET_V 0x002C
180 #define QM_PF2VF_PF_W 0x104700
181 #define QM_VF2PF_PF_R 0x104800
182 #define QM_VF2PF_VF_W 0x320
183 #define QM_PF2VF_VF_R 0x380
184 #define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
185 #define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
186 #define QM_IFC_INT_SOURCE_MASK BIT(0)
187 #define QM_IFC_INT_DISABLE BIT(0)
188 #define QM_IFC_INT_STATUS_MASK BIT(0)
189 #define QM_IFC_INT_SET_MASK BIT(0)
196 #define QM_IFC_CMD_MASK GENMASK(31, 0)
206 #define QM_CACHE_WB_START 0x204
207 #define QM_CACHE_WB_DONE 0x208
208 #define QM_FUNC_CAPS_REG 0x3100
209 #define QM_CAPBILITY_VERSION GENMASK(7, 0)
216 #define QM_PCI_COMMAND_INVALID ~0
227 #define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)
238 #define QM_QOS_TICK 0x300U
239 #define QM_QOS_DIVISOR_CLK 0x1f40U
275 SQC_VFT = 0,
286 QM_PF_FLR_PREPARE = 0x01,
298 QM_TOTAL_QP_NUM_CAP = 0x0,
311 QM_CAP_VF = 0x0,
323 {QM_CAP_VF, "QM_CAP_VF ", 0x3100, 0x0, 0x0, 0x6F01},
324 {QM_AEQE_NUM, "QM_AEQE_NUM ", 0x3104, 0x800, 0x4000800, 0x4000800},
326 0x3108, 0x4000400, 0x4000400, 0x4000400},
327 {QM_EQ_IRQ, "QM_EQ_IRQ ", 0x310c, 0x10000, 0x10000, 0x10000},
328 {QM_AEQ_IRQ, "QM_AEQ_IRQ ", 0x3110, 0x0, 0x10001, 0x10001},
329 {QM_ABNORMAL_IRQ, "QM_ABNORMAL_IRQ ", 0x3114, 0x0, 0x10003, 0x10003},
330 {QM_MB_IRQ, "QM_MB_IRQ ", 0x3118, 0x0, 0x0, 0x10002},
331 {MAX_IRQ_NUM, "MAX_IRQ_NUM ", 0x311c, 0x10001, 0x40002, 0x40003},
332 {EXT_BAR_INDEX, "EXT_BAR_INDEX ", 0x3120, 0x0, 0x0, 0x14},
336 {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0},
337 {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1},
338 {QM_SUPPORT_STOP_QP, 0x3100, 0, BIT(9), 0x0, 0x0, 0x1},
339 {QM_SUPPORT_STOP_FUNC, 0x3100, 0, BIT(10), 0x0, 0x0, 0x1},
340 {QM_SUPPORT_MB_COMMAND, 0x3100, 0, BIT(11), 0x0, 0x0, 0x1},
341 {QM_SUPPORT_SVA_PREFETCH, 0x3100, 0, BIT(14), 0x0, 0x0, 0x1},
342 {QM_SUPPORT_DAE, 0x3100, 0, BIT(15), 0x0, 0x0, 0x0},
346 {QM_SUPPORT_RPM, 0x3100, 0, BIT(13), 0x0, 0x0, 0x1},
350 {QM_SUPPORT_RPM, 0x3100, 0, BIT(12), 0x0, 0x0, 0x0},
354 {QM_TOTAL_QP_NUM_CAP, 0x100158, 0, GENMASK(10, 0), 0x1000, 0x400, 0x400},
355 {QM_FUNC_MAX_QP_CAP, 0x100158, 11, GENMASK(10, 0), 0x1000, 0x400, 0x400},
356 {QM_XEQ_DEPTH_CAP, 0x3104, 0, GENMASK(31, 0), 0x800, 0x4000800, 0x4000800},
357 {QM_QP_DEPTH_CAP, 0x3108, 0, GENMASK(31, 0), 0x4000400, 0x4000400, 0x4000400},
358 {QM_EQ_IRQ_TYPE_CAP, 0x310c, 0, GENMASK(31, 0), 0x10000, 0x10000, 0x10000},
359 {QM_AEQ_IRQ_TYPE_CAP, 0x3110, 0, GENMASK(31, 0), 0x0, 0x10001, 0x10001},
360 {QM_ABN_IRQ_TYPE_CAP, 0x3114, 0, GENMASK(31, 0), 0x0, 0x10003, 0x10003},
361 {QM_PF2VF_IRQ_TYPE_CAP, 0x3118, 0, GENMASK(31, 0), 0x0, 0x0, 0x10002},
362 {QM_PF_IRQ_NUM_CAP, 0x311c, 16, GENMASK(15, 0), 0x1, 0x4, 0x4},
363 {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3},
419 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
456 {1100, 100000, 0},
534 int delay = 0; in qm_wait_reset_finish()
543 return 0; in qm_wait_reset_finish()
576 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) | in qm_mb_pre_init()
577 (0x1 << QM_MB_BUSY_SHIFT)); in qm_mb_pre_init()
581 mailbox->rsvd = 0; in qm_mb_pre_init()
584 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
591 0x1), POLL_PERIOD, POLL_TIMEOUT); in hisi_qm_wait_mb_ready()
601 unsigned long tmp0 = 0, tmp1 = 0; in qm_mb_write()
611 asm volatile("ldp %0, %1, %3\n" in qm_mb_write()
612 "stp %0, %1, %2\n" in qm_mb_write()
648 return 0; in qm_mb_nolock()
671 /* op 0: set xqc information to hardware, 1: get xqc information from hardware. */
740 u16 randata = 0; in qm_db_v2()
782 writel(0x1, qm->io_base + QM_MEM_START_INIT); in qm_dev_mem_reset()
784 val & BIT(0), POLL_PERIOD, in qm_dev_mem_reset()
793 * @is_read: Whether read from reg, 0: not support read from reg.
857 return 0; in hisi_qm_set_algs()
869 for (i = 0; i < dev_algs_size; i++) in hisi_qm_set_algs()
875 *ptr = '\0'; in hisi_qm_set_algs()
879 return 0; in hisi_qm_set_algs()
897 return 0; in qm_pm_get_sync()
900 if (ret < 0) { in qm_pm_get_sync()
905 return 0; in qm_pm_get_sync()
923 qp->qp_status.cq_head = 0; in qm_cq_head_update()
941 qp->qp_status.cq_head, 0); in qm_poll_req_cb()
960 for (i = eqe_num - 1; i >= 0; i--) { in qm_work_process()
980 u16 cqn, eqe_num = 0; in qm_get_complete_eqe_num()
984 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_get_complete_eqe_num()
1001 qm->status.eq_head = 0; in qm_get_complete_eqe_num()
1013 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_get_complete_eqe_num()
1132 qm->status.aeq_head = 0; in qm_aeq_thread()
1139 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_aeq_thread()
1148 qp_status->sq_tail = 0; in qm_init_qp_status()
1149 qp_status->cq_head = 0; in qm_init_qp_status()
1151 atomic_set(&qp_status->used, 0); in qm_init_qp_status()
1157 u32 page_type = 0x0; in qm_init_prefetch()
1164 page_type = 0x0; in qm_init_prefetch()
1167 page_type = 0x1; in qm_init_prefetch()
1170 page_type = 0x2; in qm_init_prefetch()
1201 for (i = 0; i < table_size; i++) { in acc_shaper_calc_cbs_s()
1214 for (i = 0; i < table_size; i++) { in acc_shaper_calc_cir_s()
1219 return 0; in acc_shaper_calc_cir_s()
1231 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) { in qm_get_shaper_para()
1239 return 0; in qm_get_shaper_para()
1250 u64 tmp = 0; in qm_vft_data_cfg()
1252 if (number > 0) { in qm_vft_data_cfg()
1304 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1309 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR); in qm_set_vft_common()
1318 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_set_vft_common()
1319 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_set_vft_common()
1322 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1344 return 0; in qm_shaper_init_vft()
1366 return 0; in qm_set_sqc_cqc_vft()
1369 qm_set_vft_common(qm, i, fun_num, 0, 0); in qm_set_sqc_cqc_vft()
1379 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); in qm_get_vft_v2()
1389 return 0; in qm_get_vft_v2()
1453 writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL); in qm_hw_error_uninit_v3()
1463 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) { in qm_log_hw_error()
1468 dev_err(dev, "%s [error status=0x%x] found\n", in qm_log_hw_error()
1529 qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0); in qm_get_mb_cmd()
1578 dev_err(dev, "unsupported command(0x%x) sent by VF(%u)!\n", cmd, vf_id); in qm_handle_vf_msg()
1587 int cnt = 0; in qm_wait_vf_prepare_finish()
1588 int ret = 0; in qm_wait_vf_prepare_finish()
1593 return 0; in qm_wait_vf_prepare_finish()
1649 int cnt = 0; in qm_ping_single_vf()
1683 u64 val = 0; in qm_ping_all_vfs()
1684 int cnt = 0; in qm_ping_all_vfs()
1688 ret = qm->ops->set_ifc_begin(qm, cmd, 0, QM_MB_PING_ALL_VFS); in qm_ping_all_vfs()
1690 dev_err(dev, "failed to send command(0x%x) to all vfs!\n", cmd); in qm_ping_all_vfs()
1702 return 0; in qm_ping_all_vfs()
1722 int cnt = 0; in qm_ping_pf()
1726 ret = qm->ops->set_ifc_begin(qm, cmd, 0, 0); in qm_ping_pf()
1728 dev_err(&qm->pdev->dev, "failed to send command(0x%x) to PF!\n", cmd); in qm_ping_pf()
1754 return hisi_qm_mb(qm, QM_MB_CMD_FLUSH_QM, 0, 0, 0); in qm_drain_qm()
1759 return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0); in qm_stop_qp()
1768 0); in qm_set_msi()
1774 return 0; in qm_set_msi()
1781 return 0; in qm_set_msi()
1787 u32 cmd = ~0; in qm_wait_msi_finish()
1788 int cnt = 0; in qm_wait_msi_finish()
1833 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_msi_v3()
1836 return 0; in qm_set_msi_v3()
1843 ret = 0; in qm_set_msi_v3()
1856 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, msg, fun_num, 0); in qm_set_ifc_begin_v3()
1880 return 0; in qm_get_ifc_v3()
1898 return 0; in qm_set_ifc_begin_v4()
1934 return 0; in qm_get_ifc_v4()
1993 *addr = 0; in hisi_qm_unset_hw_reset()
2014 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC); in qm_create_qp_nolock()
2015 if (qp_id < 0) { in qm_create_qp_nolock()
2024 memset(qp->cqe, 0, sizeof(struct qm_cqe) * qp->cq_depth); in qm_create_qp_nolock()
2086 struct qm_sqc sqc = {0}; in qm_sq_ctx_cfg()
2089 sqc.dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size)); in qm_sq_ctx_cfg()
2093 sqc.w8 = 0; /* rand_qc */ in qm_sq_ctx_cfg()
2095 sqc.w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type)); in qm_sq_ctx_cfg()
2105 return qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 0); in qm_sq_ctx_cfg()
2112 struct qm_cqc cqc = {0}; in qm_cq_ctx_cfg()
2115 cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, QM_QC_CQE_SIZE)); in qm_cq_ctx_cfg()
2119 cqc.w8 = 0; /* rand_qc */ in qm_cq_ctx_cfg()
2134 return qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 0); in qm_cq_ctx_cfg()
2170 return 0; in qm_start_qp_nolock()
2178 * After this function, qp can receive request from user. Return 0 if
2210 for (i = 0; i < qp_used; i++) { in qp_stop_fail_cb()
2222 int ret, i = 0; in qm_wait_qp_empty()
2252 return 0; in qm_wait_qp_empty()
2266 u32 state = 0; in qm_drain_qp()
2271 return 0; in qm_drain_qp()
2288 return 0; in qm_drain_qp()
2357 * done function should clear used sqe to 0.
2378 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0); in hisi_qp_send()
2382 return 0; in hisi_qp_send()
2393 writel(0x1, qm->io_base + QM_CACHE_WB_START); in hisi_qm_cache_wb()
2395 val, val & BIT(0), POLL_PERIOD, in hisi_qm_cache_wb()
2422 for (i = 0; i < qm->qp_num; i++) in hisi_qm_set_hw_reset()
2432 u8 alg_type = 0; in hisi_qm_uacce_get_queue()
2445 return 0; in hisi_qm_uacce_get_queue()
2494 * dma_mmap_coherent() requires vm_pgoff as 0 in hisi_qm_uacce_mmap()
2498 vma->vm_pgoff = 0; in hisi_qm_uacce_mmap()
2521 u32 i = 0; in hisi_qm_uacce_stop_queue()
2549 int updated = 0; in hisi_qm_is_q_updated()
2594 return 0; in hisi_qm_uacce_ioctl()
2608 return 0; in hisi_qm_uacce_ioctl()
2623 u32 count = 0; in qm_hw_err_isolate()
2631 return 0; in qm_hw_err_isolate()
2660 return 0; in qm_hw_err_isolate()
2705 return 0; in hisi_qm_isolate_threshold_write()
2761 if (ret < 0) in qm_alloc_uacce()
2808 return 0; in qm_alloc_uacce()
2821 return 0; in qm_frozen()
2829 return 0; in qm_frozen()
2842 int ret = 0; in qm_try_frozen_vfs()
2898 for (i = num - 1; i >= 0; i--) { in hisi_qp_memory_uninit()
2937 return 0; in hisi_qp_memory_init()
2961 qm->qp_in_used = 0; in hisi_qm_pre_init()
3110 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3112 * (VF function number 0x2)
3130 status->eq_head = 0; in qm_init_eq_aeq_status()
3131 status->aeq_head = 0; in qm_init_eq_aeq_status()
3139 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_enable_eq_aeq_interrupts()
3140 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_enable_eq_aeq_interrupts()
3142 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK); in qm_enable_eq_aeq_interrupts()
3143 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK); in qm_enable_eq_aeq_interrupts()
3148 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK); in qm_disable_eq_aeq_interrupts()
3149 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK); in qm_disable_eq_aeq_interrupts()
3154 struct qm_eqc eqc = {0}; in qm_eq_ctx_cfg()
3162 return qm_set_and_get_xqc(qm, QM_MB_CMD_EQC, &eqc, 0, 0); in qm_eq_ctx_cfg()
3167 struct qm_aeqc aeqc = {0}; in qm_aeq_ctx_cfg()
3173 return qm_set_and_get_xqc(qm, QM_MB_CMD_AEQC, &aeqc, 0, 0); in qm_aeq_ctx_cfg()
3199 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num); in __hisi_qm_start()
3208 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); in __hisi_qm_start()
3212 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); in __hisi_qm_start()
3219 return 0; in __hisi_qm_start()
3231 int ret = 0; in hisi_qm_start()
3238 dev_err(dev, "qp_num should not be 0\n"); in hisi_qm_start()
3263 if (ret < 0) in qm_restart()
3267 for (i = 0; i < qm->qp_num; i++) { in qm_restart()
3271 ret = qm_start_qp_nolock(qp, 0); in qm_restart()
3272 if (ret < 0) { in qm_restart()
3283 return 0; in qm_restart()
3292 for (i = 0; i < qm->qp_num; i++) { in qm_stop_started_qp()
3313 for (i = 0; i < qm->qp_num; i++) { in qm_clear_queues()
3316 memset(qp->qdma.va, 0, qp->qdma.size); in qm_clear_queues()
3319 memset(qm->qdma.va, 0, qm->qdma.size); in qm_clear_queues()
3334 int ret = 0; in hisi_qm_stop()
3368 ret = hisi_qm_set_vft(qm, 0, 0, 0); in hisi_qm_stop()
3369 if (ret < 0) { in hisi_qm_stop()
3466 if (!qps || qp_num <= 0) in hisi_qm_free_qps()
3469 for (i = qp_num - 1; i >= 0; i--) in hisi_qm_free_qps()
3497 if (dev_node < 0) in hisi_qm_sort_devices()
3498 dev_node = 0; in hisi_qm_sort_devices()
3516 return 0; in hisi_qm_sort_devices()
3539 if (!qps || !qm_list || qp_num <= 0) in hisi_qm_alloc_qps_node()
3549 for (i = 0; i < qp_num; i++) { in hisi_qm_alloc_qps_node()
3558 ret = 0; in hisi_qm_alloc_qps_node()
3593 for (i = num_vfs; i > 0; i--) { in qm_vf_q_assign()
3600 remain_q_num = 0; in qm_vf_q_assign()
3601 } else if (remain_q_num > 0) { in qm_vf_q_assign()
3612 hisi_qm_set_vft(qm, j, 0, 0); in qm_vf_q_assign()
3618 return 0; in qm_vf_q_assign()
3627 ret = hisi_qm_set_vft(qm, i, 0, 0); in qm_clear_vft_config()
3631 qm->vfs_num = 0; in qm_clear_vft_config()
3633 return 0; in qm_clear_vft_config()
3663 return 0; in qm_func_shaper_enable()
3668 u64 cir_u = 0, cir_b = 0, cir_s = 0; in qm_get_shaper_vft_qos()
3675 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
3678 return 0; in qm_get_shaper_vft_qos()
3680 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR); in qm_get_shaper_vft_qos()
3684 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_get_shaper_vft_qos()
3685 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_get_shaper_vft_qos()
3688 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
3691 return 0; in qm_get_shaper_vft_qos()
3710 return 0; in qm_get_shaper_vft_qos()
3730 dev_err(dev, "failed to send command(0x%x) to VF(%u)!\n", QM_PF_SET_QOS, fun_num); in qm_vf_get_qos()
3735 int cnt = 0; in qm_vf_read_qos()
3739 qm->mb_qos = 0; in qm_vf_read_qos()
3782 ir = qm_get_shaper_vft_qos(qm, 0); in qm_algqos_read()
3807 char tbuf_bdf[QM_DBG_READ_LEN] = {0}; in qm_get_qos_value()
3808 char val_buf[QM_DBG_READ_LEN] = {0}; in qm_get_qos_value()
3818 if (ret || *val == 0 || *val > QM_QOS_MAX_VAL) { in qm_get_qos_value()
3833 return 0; in qm_get_qos_value()
3845 if (*pos != 0) in qm_algqos_write()
3846 return 0; in qm_algqos_write()
3852 if (len < 0) in qm_algqos_write()
3855 tbuf[len] = '\0'; in qm_algqos_write()
4006 qm->vfs_num = 0; in hisi_qm_sriov_disable()
4018 * Enable SR-IOV according to num_vfs, 0 means disable.
4022 if (num_vfs == 0) in hisi_qm_sriov_configure()
4090 return 0; in qm_check_req_recv()
4124 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_pf_mse()
4127 return 0; in qm_set_pf_mse()
4144 * pci_find_ext_capability cannot return 0, pos does not need to be in qm_set_vf_mse()
4155 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_vf_mse()
4159 return 0; in qm_set_vf_mse()
4169 u32 nfe_enb = 0; in qm_dev_ecc_mbit_handle()
4196 int ret = 0; in qm_vf_reset_prepare()
4226 return 0; in qm_try_stop_vfs()
4288 return 0; in qm_controller_reset_prepare()
4351 unsigned long long value = 0; in qm_reset_device()
4367 return 0; in qm_reset_device()
4391 int ret = 0; in qm_vf_reset_done()
4420 return 0; in qm_try_start_vfs()
4560 return 0; in qm_controller_reset_done()
4592 return 0; in qm_controller_reset()
4634 u32 delay = 0; in hisi_qm_reset_prepare()
4852 val == BIT(0), QM_VF_RESET_WAIT_US, in qm_wait_pf_reset_finish()
4864 ret = qm->ops->get_ifc(qm, &cmd, NULL, 0); in qm_wait_pf_reset_finish()
4865 qm_clear_cmd_interrupt(qm, 0); in qm_wait_pf_reset_finish()
4872 dev_err(dev, "the command(0x%x) is not reset done!\n", cmd); in qm_wait_pf_reset_finish()
4938 dev_err(dev, "unsupported command(0x%x) sent by function(%u)!\n", cmd, fun_num); in qm_handle_cmd_msg()
4964 qm_handle_cmd_msg(qm, 0); in qm_cmd_process()
4981 return 0; in hisi_qm_alg_register()
4986 return 0; in hisi_qm_alg_register()
5036 return 0; in qm_register_abnormal_irq()
5040 return 0; in qm_register_abnormal_irq()
5043 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_abnormal_irq, 0, qm->dev_name, qm); in qm_register_abnormal_irq()
5071 return 0; in qm_register_mb_cmd_irq()
5074 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_mb_cmd_irq, 0, qm->dev_name, qm); in qm_register_mb_cmd_irq()
5102 return 0; in qm_register_aeq_irq()
5134 return 0; in qm_register_eq_irq()
5137 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_eq_irq, 0, qm->dev_name, qm); in qm_register_eq_irq()
5172 return 0; in qm_irqs_register()
5194 return 0; in qm_get_qp_num()
5203 return 0; in qm_get_qp_num()
5217 return 0; in qm_get_qp_num()
5231 for (i = 0; i < size; i++) { in qm_pre_store_caps()
5241 return 0; in qm_pre_store_caps()
5270 for (i = 0; i < size; i++) { in qm_get_hw_caps()
5301 if (ret < 0) { in qm_get_pci_res()
5331 qm->db_interval = 0; in qm_get_pci_res()
5339 return 0; in qm_get_pci_res()
5357 return 0; in qm_clear_device()
5361 return 0; in qm_clear_device()
5365 return 0; in qm_clear_device()
5369 return 0; in qm_clear_device()
5373 writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL); in qm_clear_device()
5380 writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL); in qm_clear_device()
5396 if (ret < 0) { in hisi_qm_pci_init()
5406 if (ret < 0) in hisi_qm_pci_init()
5412 if (ret < 0) { in hisi_qm_pci_init()
5421 return 0; in hisi_qm_pci_init()
5436 for (i = 0; i < qm->qp_num; i++) in hisi_qm_init_work()
5453 return 0; in hisi_qm_init_work()
5478 for (i = 0; i < qm->qp_num; i++) { in hisi_qp_alloc_memory()
5487 return 0; in hisi_qp_alloc_memory()
5499 size_t off = 0; in hisi_qm_alloc_rsv_buf()
5505 } while (0) in hisi_qm_alloc_rsv_buf()
5521 return 0; in hisi_qm_alloc_rsv_buf()
5528 size_t off = 0; in hisi_qm_memory_init()
5537 qm->factor[0].func_qos = QM_QOS_MAX_VAL; in hisi_qm_memory_init()
5544 } while (0) in hisi_qm_memory_init()
5573 return 0; in hisi_qm_memory_init()
5620 if (ret < 0) in hisi_qm_init()
5634 return 0; in hisi_qm_init()
5834 return 0; in hisi_qm_resume()