Lines Matching +full:switching +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
24 #include "cpufreq-dt.h"
111 static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq) in armada_37xx_cpu_freq_info_get() argument
116 if (freq == armada_37xx_dvfs[i].cpu_freq_max) in armada_37xx_cpu_freq_info_get()
120 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); in armada_37xx_cpu_freq_info_get()
162 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
183 * the round-up closest to the target voltage value.
189 /* Find out the round-up closest supported voltage value */ in armada_37xx_avs_val_match()
199 avs = ARRAY_SIZE(avs_map) - 1; in armada_37xx_avs_val_match()
207 * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
209 * - L1 voltage should be about 100mv smaller than L0 voltage
210 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
234 dvfs->avs[0] = l0_vdd_min; in armada37xx_cpufreq_avs_configure()
244 dvfs->avs[load_level] = avs_min; in armada37xx_cpufreq_avs_configure()
251 if (dvfs->cpu_freq_max >= 1000*1000*1000) { in armada37xx_cpufreq_avs_configure()
252 if (dvfs->cpu_freq_max >= 1200*1000*1000) in armada37xx_cpufreq_avs_configure()
256 dvfs->avs[0] = dvfs->avs[1] = avs_min; in armada37xx_cpufreq_avs_configure()
263 * L1 voltage is equal to L0 voltage - 100mv and it must be in armada37xx_cpufreq_avs_configure()
267 target_vm = avs_map[l0_vdd_min] - 100; in armada37xx_cpufreq_avs_configure()
269 dvfs->avs[1] = armada_37xx_avs_val_match(target_vm); in armada37xx_cpufreq_avs_configure()
272 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must in armada37xx_cpufreq_avs_configure()
275 target_vm = avs_map[l0_vdd_min] - 150; in armada37xx_cpufreq_avs_configure()
277 dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm); in armada37xx_cpufreq_avs_configure()
281 * otherwise the CPU gets stuck when switching from load L1 to load L0. in armada37xx_cpufreq_avs_configure()
284 if (dvfs->cpu_freq_max >= 1000*1000*1000) { in armada37xx_cpufreq_avs_configure()
287 if (dvfs->cpu_freq_max >= 1200*1000*1000) in armada37xx_cpufreq_avs_configure()
292 if (avs_min_l1 > dvfs->avs[0]) in armada37xx_cpufreq_avs_configure()
293 avs_min_l1 = dvfs->avs[0]; in armada37xx_cpufreq_avs_configure()
295 if (dvfs->avs[1] < avs_min_l1) in armada37xx_cpufreq_avs_configure()
296 dvfs->avs[1] = avs_min_l1; in armada37xx_cpufreq_avs_configure()
321 avs_val = dvfs->avs[load_level]; in armada37xx_cpufreq_avs_setup()
322 regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1), in armada37xx_cpufreq_avs_setup()
366 regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1); in armada37xx_cpufreq_suspend()
367 regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3); in armada37xx_cpufreq_suspend()
368 regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD, in armada37xx_cpufreq_suspend()
369 &state->nb_cpu_load); in armada37xx_cpufreq_suspend()
370 regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod); in armada37xx_cpufreq_suspend()
380 armada37xx_cpufreq_disable_dvfs(state->regmap); in armada37xx_cpufreq_resume()
382 regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1); in armada37xx_cpufreq_resume()
383 regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3); in armada37xx_cpufreq_resume()
384 regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD, in armada37xx_cpufreq_resume()
385 state->nb_cpu_load); in armada37xx_cpufreq_resume()
392 regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod); in armada37xx_cpufreq_resume()
402 unsigned long freq; in armada37xx_cpufreq_driver_init() local
410 syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb"); in armada37xx_cpufreq_driver_init()
412 return -ENODEV; in armada37xx_cpufreq_driver_init()
415 syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm"); in armada37xx_cpufreq_driver_init()
418 return -ENODEV; in armada37xx_cpufreq_driver_init()
421 syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs"); in armada37xx_cpufreq_driver_init()
439 return -ENODEV; in armada37xx_cpufreq_driver_init()
461 return -EINVAL; in armada37xx_cpufreq_driver_init()
467 return -EINVAL; in armada37xx_cpufreq_driver_init()
474 return -ENOMEM; in armada37xx_cpufreq_driver_init()
477 armada37xx_cpufreq_state->regmap = nb_pm_base; in armada37xx_cpufreq_driver_init()
482 armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider); in armada37xx_cpufreq_driver_init()
487 unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000; in armada37xx_cpufreq_driver_init()
488 freq = base_frequency / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_init()
489 ret = dev_pm_opp_add(cpu_dev, freq, u_volt); in armada37xx_cpufreq_driver_init()
503 pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata, in armada37xx_cpufreq_driver_init()
509 armada37xx_cpufreq_state->cpu_dev = cpu_dev; in armada37xx_cpufreq_driver_init()
510 armada37xx_cpufreq_state->pdev = pdev; in armada37xx_cpufreq_driver_init()
517 /* clean-up the already added opp before leaving */ in armada37xx_cpufreq_driver_init()
518 while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) { in armada37xx_cpufreq_driver_init()
519 freq = base_frequency / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_init()
520 dev_pm_opp_remove(cpu_dev, freq); in armada37xx_cpufreq_driver_init()
532 struct platform_device *pdev = armada37xx_cpufreq_state->pdev; in armada37xx_cpufreq_driver_exit()
534 unsigned long freq; in armada37xx_cpufreq_driver_exit() local
539 armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap); in armada37xx_cpufreq_driver_exit()
542 freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_exit()
543 dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq); in armada37xx_cpufreq_driver_exit()
551 { .compatible = "marvell,armada-3700-nb-pm" },
556 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");