Kconfig - OpenGrok cross reference for /linux-6.15/drivers/clocksource/Kconfig

1 # SPDX-License-Identifier: GPL-2.0-only
60 	bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 	  Enables the support for the TI dual-mode timer driver.
190 	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
211 	  Support for Multi Timer Unit. MTU provides access
213 	  32-bit free running decrementing counters.
248 	bool "Integrator-AP timer driver" if COMPILE_TEST
251 	  Enables support for the Integrator-AP timer.
276 	  available on many OMAP-like platforms.
295 	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
299 	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
304 	bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
308 	  This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
326 	  power-of-2 divisor of the clock rate. The behaviour can also be
329 	  The main use of the event stream is wfe-based timeouts of userspace
340 	bool "Workaround for Freescale/NXP Erratum A-008585"
346 	  A-008585 ("ARM generic timer may contain an erroneous
348 	  fsl,erratum-a008585 property is found in the timer node.
357 	  161010101. The workaround will be active if the hisilicon,erratum-161010101
361 	bool "Workaround for Cortex-A73 erratum 858921"
366 	  This option enables a workaround applicable to Cortex-A73
379 	  allwinner,erratum-unknown1 property is found in the timer node.
417 	bool "Support for the ARMv7M system time" if COMPILE_TEST
421 	  This option enables support for the ARMv7M system timer unit.
446 	bool "Exynos multi core timer driver" if COMPILE_TEST
450 	  Support for Multi Core Timer controller on Exynos SoCs.
514 	bool "J-Core PIT timer driver" if COMPILE_TEST
520 	  the integrated PIT in the J-Core synthesizable, open source SoC.
528 	  the Compare Match Timer (CMT) hardware available in 16/32/48-bit
536 	  This enables build of a clockevent driver for the Multi-Function
538 	  This hardware comes with 16-bit timer registers.
554 	  the 32-bit Timer Unit (TMU) hardware available on a wide range
563 	  the 48-bit System Timer (STI) hardware available on a SoCs
581 	  counter available in the "System Registers" block of
591 	bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
595 	  This enables OST0 support available on PXA and SA-11x0
613 	bool "i.MX system counter timer" if COMPILE_TEST
616 	  Enable this option to use i.MX system counter timer as a
646 	bool "Timer for the RISC-V platform" if COMPILE_TEST
651 	  This enables the per-hart timer built into all RISC-V systems, which
653 	  required for all RISC-V systems.
656 	bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
661 	  This option enables the CLINT timer for RISC-V systems.  The CLINT
662 	  driver is usually used for NoMMU RISC-V systems.
665 	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
669 	  Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
670 	  system.
671 	  csky,mptimer is not only used in SMP system, it also could be used in
672 	  single core system. It's not a mmio reg and it uses mtcr/mfcr instruction.
675 	bool "Gx6605s SOC system timer driver" if COMPILE_TEST
698 	  programmable 32-bit free running incrementing counters.
727 	  Support for the Operating System Timer of the Ingenic JZ SoCs.
735 	  based system. It supports the oneshot, the periodic
740 	bool "Clocksource using goldfish-rtc"
744 	  Support for the timer/counter of goldfish-rtc
758 	bool "Ralink System Tick Counter"
763 	  Enables support for system tick counter present on