Lines Matching +full:reg +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
13 static unsigned int next_div(unsigned int div, bool shift) in next_div() argument
15 if (shift) in next_div()
22 bool shift, in ccu_mp_find_best() argument
29 for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) { in ccu_mp_find_best()
36 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
55 bool shift) in ccu_mp_find_best_with_parent_adj() argument
72 for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) { in ccu_mp_find_best_with_parent_adj()
115 bool shift = true; in ccu_mp_round_rate() local
117 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_round_rate()
118 rate *= cmp->fixed_post_div; in ccu_mp_round_rate()
120 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) in ccu_mp_round_rate()
121 shift = false; in ccu_mp_round_rate()
123 max_m = cmp->m.max ?: 1 << cmp->m.width; in ccu_mp_round_rate()
124 if (shift) in ccu_mp_round_rate()
125 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); in ccu_mp_round_rate()
127 max_p = cmp->p.max ?: 1 << cmp->p.width; in ccu_mp_round_rate()
129 if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) { in ccu_mp_round_rate()
130 rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, shift, in ccu_mp_round_rate()
134 max_m, max_p, shift); in ccu_mp_round_rate()
137 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_round_rate()
138 rate /= cmp->fixed_post_div; in ccu_mp_round_rate()
147 return ccu_gate_helper_disable(&cmp->common, cmp->enable); in ccu_mp_disable()
154 return ccu_gate_helper_enable(&cmp->common, cmp->enable); in ccu_mp_enable()
161 return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable); in ccu_mp_is_enabled()
170 u32 reg; in ccu_mp_recalc_rate() local
172 /* Adjust parent_rate according to pre-dividers */ in ccu_mp_recalc_rate()
173 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, in ccu_mp_recalc_rate()
176 reg = readl(cmp->common.base + cmp->common.reg); in ccu_mp_recalc_rate()
178 m = reg >> cmp->m.shift; in ccu_mp_recalc_rate()
179 m &= (1 << cmp->m.width) - 1; in ccu_mp_recalc_rate()
180 m += cmp->m.offset; in ccu_mp_recalc_rate()
184 p = reg >> cmp->p.shift; in ccu_mp_recalc_rate()
185 p &= (1 << cmp->p.width) - 1; in ccu_mp_recalc_rate()
187 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) in ccu_mp_recalc_rate()
192 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_recalc_rate()
193 rate /= cmp->fixed_post_div; in ccu_mp_recalc_rate()
203 return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux, in ccu_mp_determine_rate()
214 bool shift = true; in ccu_mp_set_rate() local
215 u32 reg; in ccu_mp_set_rate() local
217 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) in ccu_mp_set_rate()
218 shift = false; in ccu_mp_set_rate()
220 /* Adjust parent_rate according to pre-dividers */ in ccu_mp_set_rate()
221 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, in ccu_mp_set_rate()
224 max_m = cmp->m.max ?: 1 << cmp->m.width; in ccu_mp_set_rate()
225 if (shift) in ccu_mp_set_rate()
226 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); in ccu_mp_set_rate()
228 max_p = cmp->p.max ?: 1 << cmp->p.width; in ccu_mp_set_rate()
230 /* Adjust target rate according to post-dividers */ in ccu_mp_set_rate()
231 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) in ccu_mp_set_rate()
232 rate = rate * cmp->fixed_post_div; in ccu_mp_set_rate()
234 ccu_mp_find_best(parent_rate, rate, max_m, max_p, shift, &m, &p); in ccu_mp_set_rate()
236 spin_lock_irqsave(cmp->common.lock, flags); in ccu_mp_set_rate()
238 reg = readl(cmp->common.base + cmp->common.reg); in ccu_mp_set_rate()
239 reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); in ccu_mp_set_rate()
240 reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift); in ccu_mp_set_rate()
241 reg |= (m - cmp->m.offset) << cmp->m.shift; in ccu_mp_set_rate()
242 if (shift) in ccu_mp_set_rate()
243 reg |= ilog2(p) << cmp->p.shift; in ccu_mp_set_rate()
245 reg |= (p - cmp->p.offset) << cmp->p.shift; in ccu_mp_set_rate()
247 writel(reg, cmp->common.base + cmp->common.reg); in ccu_mp_set_rate()
249 spin_unlock_irqrestore(cmp->common.lock, flags); in ccu_mp_set_rate()
258 return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux); in ccu_mp_get_parent()
265 return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index); in ccu_mp_set_parent()
304 u32 val = readl(cm->base + cm->reg); in ccu_mp_mmc_recalc_rate()
315 u32 val = readl(cm->base + cm->reg); in ccu_mp_mmc_determine_rate()
320 req->rate *= 2; in ccu_mp_mmc_determine_rate()
321 req->min_rate *= 2; in ccu_mp_mmc_determine_rate()
322 req->max_rate *= 2; in ccu_mp_mmc_determine_rate()
327 /* re-adjust the requested clock rate back */ in ccu_mp_mmc_determine_rate()
329 req->rate /= 2; in ccu_mp_mmc_determine_rate()
330 req->min_rate /= 2; in ccu_mp_mmc_determine_rate()
331 req->max_rate /= 2; in ccu_mp_mmc_determine_rate()
341 u32 val = readl(cm->base + cm->reg); in ccu_mp_mmc_set_rate()