Lines Matching +full:24 +full:m
31 * The 24 MHz oscillator, the root of most of the clock tree.
49 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
70 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
97 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
99 static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M",
104 static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M",
106 static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M",
108 static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M",
110 static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M",
112 static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M",
114 static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M",
125 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
139 static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M",
141 static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M",
147 static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M",
149 static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M",
151 static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M",
153 static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M",
155 static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M",
160 static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M",
168 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
183 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
205 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
227 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
249 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
264 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
282 * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
286 * The M factor must be an even number to produce a 50% duty cycle output.
290 { .rate = 90316800, .pattern = 0xc000872b, .m = 20, .n = 75 },
291 { .rate = 98304000, .pattern = 0xc0004dd3, .m = 12, .n = 49 },
299 .m = _SUNXI_CCU_DIV(16, 6),
300 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
323 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
350 0, 5, /* M */
351 24, 2, /* mux */
356 0, 5, /* M */
357 24, 2, /* mux */
369 0, 5, /* M */
370 24, 3, /* mux */
384 0, 5, /* M */
386 24, 3, /* mux */
404 0, 5, /* M */
405 24, 3, /* mux */
419 0, 5, /* M */
420 24, 3, /* mux */
434 0, 5, /* M */
435 24, 3, /* mux */
451 0, 4, /* M */
452 24, 3, /* mux */
465 0, 5, /* M */
466 24, 3, /* mux */
481 0, 5, /* M */
482 24, 3, /* mux */
504 0, 0, /* M */
506 24, 3, /* mux */
513 0, 0, /* M */
515 24, 3, /* mux */
522 0, 0, /* M */
524 24, 3, /* mux */
531 0, 0, /* M */
533 24, 3, /* mux */
540 0, 0, /* M */
542 24, 3, /* mux */
549 0, 0, /* M */
551 24, 3, /* mux */
575 0, 5, /* M */
577 24, 3, /* mux */
594 0, 5, /* M */
596 24, 3, /* mux */
631 0, 5, /* M */
632 24, 3, /* mux */
638 0, 5, /* M */
639 24, 3, /* mux */
648 0, 5, /* M */
650 24, 3, /* mux */
657 0, 5, /* M */
659 24, 3, /* mux */
674 0, 5, /* M */
676 24, 3, /* mux */
722 0, 5, /* M */
724 24, 3, /* mux */
728 0, 5, /* M */
730 24, 3, /* mux */
734 0, 5, /* M */
736 24, 3, /* mux */
740 0, 5, /* M */
742 24, 3, /* mux */
751 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac0_25M_clk, "emac0-25M",
754 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac1_25M_clk, "emac1-25M",
768 0, 5, /* M */
769 24, 1, /* mux */
781 0, 5, /* M */
782 24, 1, /* mux */
789 0, 5, /* M */
793 0, 5, /* M */
822 .shift = 24,
840 .shift = 24,
875 0, 5, /* M */
876 24, 1, /* mux */
885 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0);
897 24, 1, /* mux */
910 0, 5, /* M */
911 24, 3, /* mux */
917 0, 5, /* M */
918 24, 3, /* mux */
939 0, 5, /* M */
940 24, 3, /* mux */
946 0, 5, /* M */
947 24, 3, /* mux */
960 0, 5, /* M */
961 24, 3, /* mux */
967 0, 5, /* M */
968 24, 3, /* mux */
974 0, 5, /* M */
975 24, 3, /* mux */
988 0, 4, /* M */
989 24, 3, /* mux */
995 0, 4, /* M */
996 24, 3, /* mux */
1013 0, 4, /* M */
1014 24, 3, /* mux */
1022 0, 4, /* M */
1023 24, 1, /* mux */
1038 0, 5, /* M */
1039 24, 3, /* mux */
1052 0, 5, /* M */
1054 24, 3, /* mux */
1060 0, 5, /* M */
1062 24, 3, /* mux */
1068 0, 5, /* M */
1070 24, 3, /* mux */
1076 0, 5, /* M */
1078 24, 3, /* mux */
1091 0, 5, /* M */
1092 24, 3, /* mux */
1104 0, 5, /* M */
1105 24, 3, /* mux */
1109 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
1111 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
1113 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M",
1116 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M",
1119 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M",
1121 0xf30, BIT(4), 24, 0);
1129 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M",
1133 24, 2, /* mux */
1585 [RST_BUS_OTG] = { 0xa8c, BIT(24) },