Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
28 #include "ccu-sun55i-a523.h"
31 * The 24 MHz oscillator, the root of most of the clock tree.
32 * .fw_name is the string used in the DT "clock-names" property, used to
46 .enable = BIT(27),
47 .lock = BIT(28),
53 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
67 .enable = BIT(27),
68 .lock = BIT(28),
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x",
79 * Most clock-defining macros expect an *array* of parent clocks, even if
82 * a single-entry array out of that. The macros using _HWS take such an
92 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
97 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
99 static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M",
104 static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M",
106 static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M",
108 static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M",
110 static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M",
112 static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M",
114 static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M",
122 .enable = BIT(27),
123 .lock = BIT(28),
128 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph1-4x",
137 static SUNXI_CCU_M_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
139 static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M",
141 static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M",
147 static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M",
149 static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M",
151 static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M",
153 static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M",
155 static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M",
160 static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M",
165 .enable = BIT(27),
166 .lock = BIT(28),
172 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-gpu", osc24M,
180 .enable = BIT(27),
181 .lock = BIT(28),
186 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-8x",
195 static SUNXI_CCU_M_HWS(pll_video0_4x_clk, "pll-video0-4x",
197 static CLK_FIXED_FACTOR_HWS(pll_video0_3x_clk, "pll-video0-3x",
202 .enable = BIT(27),
203 .lock = BIT(28),
208 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-8x",
217 static SUNXI_CCU_M_HWS(pll_video1_4x_clk, "pll-video1-4x",
219 static CLK_FIXED_FACTOR_HWS(pll_video1_3x_clk, "pll-video1-3x",
224 .enable = BIT(27),
225 .lock = BIT(28),
230 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video2-8x",
239 static SUNXI_CCU_M_HWS(pll_video2_4x_clk, "pll-video2-4x",
241 static CLK_FIXED_FACTOR_HWS(pll_video2_3x_clk, "pll-video2-3x",
246 .enable = BIT(27),
247 .lock = BIT(28),
253 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
261 .enable = BIT(27),
262 .lock = BIT(28),
267 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video3-8x",
276 static SUNXI_CCU_M_HWS(pll_video3_4x_clk, "pll-video3-4x",
278 static CLK_FIXED_FACTOR_HWS(pll_video3_3x_clk, "pll-video3-3x",
296 .enable = BIT(27),
297 .lock = BIT(28),
300 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
301 0x178, BIT(31)),
307 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x",
313 static CLK_FIXED_FACTOR_HW(pll_audio0_2x_clk, "pll-audio0-2x",
315 static CLK_FIXED_FACTOR_HW(pll_audio0_clk, "pll-audio0",
320 .enable = BIT(27),
321 .lock = BIT(28),
326 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-npu-4x",
331 static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x",
334 static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x",
351 24, 2, /* mux */
357 24, 2, /* mux */
370 24, 3, /* mux */
386 24, 3, /* mux */
387 BIT(31), /* gate */
405 24, 3, /* mux */
406 BIT(31), /* gate */
409 static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws, 0x60c, BIT(0), 0);
420 24, 3, /* mux */
421 BIT(31), /* gate */
424 static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0x62c, BIT(0), 0);
435 24, 3, /* mux */
436 BIT(31), /* gate */
439 static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0x63c, BIT(0), 0);
452 24, 3, /* mux */
453 BIT(31), /* gate */
456 static SUNXI_CCU_GATE_HWS(bus_gpu_clk, "bus-gpu", ahb_hws, 0x67c, BIT(0), 0);
466 24, 3, /* mux */
467 BIT(31), /* gate */
470 static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0x68c, BIT(0), 0);
471 static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0x68c,
472 BIT(1), 0);
482 24, 3, /* mux */
483 BIT(31), /* gate */
486 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0);
488 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0);
490 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c,
491 BIT(0), 0);
493 static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, 0x72c,
494 BIT(0), 0);
506 24, 3, /* mux */
507 BIT(31), /* gate */
515 24, 3, /* mux */
516 BIT(31), /* gate */
524 24, 3, /* mux */
525 BIT(31), /* gate */
533 24, 3, /* mux */
534 BIT(31), /* gate */
542 24, 3, /* mux */
543 BIT(31), /* gate */
551 24, 3, /* mux */
552 BIT(31), /* gate */
555 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c,
556 BIT(0), 0);
558 static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws, 0x78c,
559 BIT(0), 0);
561 static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb1_hws, 0x7ac, BIT(0), 0);
562 static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb1_hws, 0x7ac, BIT(1), 0);
577 24, 3, /* mux */
578 BIT(31), /* gate */
582 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc,
583 BIT(0), 0);
596 24, 3, /* mux */
597 BIT(31), /* gate */
601 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
602 0x804, BIT(0), 0);
603 static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
604 0x804, BIT(1), 0);
605 static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
606 0x804, BIT(2), 0);
607 static SUNXI_CCU_GATE_HWS(mbus_nand_clk, "mbus-nand", mbus_hws,
608 0x804, BIT(5), 0);
609 static SUNXI_CCU_GATE_HWS(mbus_usb3_clk, "mbus-usb3", mbus_hws,
610 0x804, BIT(6), 0);
611 static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
612 0x804, BIT(8), 0);
613 static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
614 0x804, BIT(9), 0);
615 static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws,
616 0x804, BIT(12), 0);
618 static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws, 0x80c,
619 BIT(0), CLK_IS_CRITICAL);
632 24, 3, /* mux */
633 BIT(31), /* gate */
639 24, 3, /* mux */
640 BIT(31), /* gate */
643 static SUNXI_CCU_GATE_HWS(bus_nand_clk, "bus-nand", ahb_hws, 0x82c,
644 BIT(0), 0);
650 24, 3, /* mux */
651 BIT(31), /* gate */
659 24, 3, /* mux */
660 BIT(31), /* gate */
676 24, 3, /* mux */
677 BIT(31), /* gate */
681 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws, 0x84c, BIT(0), 0);
682 static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws, 0x84c, BIT(1), 0);
683 static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws, 0x84c, BIT(2), 0);
685 static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, 0x88c,
686 BIT(0), 0);
688 static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws, 0x90c,
689 BIT(0), 0);
690 static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws, 0x90c,
691 BIT(1), 0);
692 static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws, 0x90c,
693 BIT(2), 0);
694 static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws, 0x90c,
695 BIT(3), 0);
696 static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws, 0x90c,
697 BIT(4), 0);
698 static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws, 0x90c,
699 BIT(5), 0);
700 static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb1_hws, 0x90c,
701 BIT(6), 0);
702 static SUNXI_CCU_GATE_HWS(bus_uart7_clk, "bus-uart7", apb1_hws, 0x90c,
703 BIT(7), 0);
705 static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0x91c, BIT(0), 0);
706 static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0x91c, BIT(1), 0);
707 static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0x91c, BIT(2), 0);
708 static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0x91c, BIT(3), 0);
709 static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0x91c, BIT(4), 0);
710 static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0x91c, BIT(5), 0);
712 static SUNXI_CCU_GATE_HWS(bus_can_clk, "bus-can", apb1_hws, 0x92c, BIT(0), 0);
724 24, 3, /* mux */
725 BIT(31), /* gate */
730 24, 3, /* mux */
731 BIT(31), /* gate */
736 24, 3, /* mux */
737 BIT(31), /* gate */
742 24, 3, /* mux */
743 BIT(31), /* gate */
745 static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws, 0x96c, BIT(0), 0);
746 static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws, 0x96c, BIT(1), 0);
747 static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws, 0x96c, BIT(2), 0);
748 static SUNXI_CCU_GATE_HWS(bus_spifc_clk, "bus-spifc", ahb_hws, 0x96c,
749 BIT(3), 0);
751 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac0_25M_clk, "emac0-25M",
753 0x970, BIT(31) | BIT(30), 6, 0);
754 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac1_25M_clk, "emac1-25M",
756 0x974, BIT(31) | BIT(30), 6, 0);
757 static SUNXI_CCU_GATE_HWS(bus_emac0_clk, "bus-emac0", ahb_hws, 0x97c,
758 BIT(0), 0);
759 static SUNXI_CCU_GATE_HWS(bus_emac1_clk, "bus-emac1", ahb_hws, 0x98c,
760 BIT(0), 0);
767 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_rx_parents, 0x990,
769 24, 1, /* mux */
770 BIT(31), /* gate */
772 static SUNXI_CCU_GATE_HWS(bus_ir_rx_clk, "bus-ir-rx", apb0_hws, 0x99c,
773 BIT(0), 0);
779 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents,
782 24, 1, /* mux */
783 BIT(31), /* gate */
785 static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws, 0x9cc,
786 BIT(0), 0);
790 BIT(31), /* gate */
794 BIT(31), /* gate */
796 static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0x9ec,
797 BIT(0), 0);
798 static SUNXI_CCU_GATE_HWS(bus_gpadc1_clk, "bus-gpadc1", ahb_hws, 0x9ec,
799 BIT(1), 0);
801 static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws, 0x9fc, BIT(0), 0);
805 * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
820 .enable = BIT(31),
822 .shift = 24,
830 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
838 .enable = BIT(31),
840 .shift = 24,
848 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
855 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0xa8c,
856 BIT(0), 0);
857 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0xa8c,
858 BIT(1), 0);
859 static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0xa8c,
860 BIT(4), 0);
861 static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0xa8c,
862 BIT(5), 0);
863 static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
865 static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0xa9c,
866 BIT(0), 0);
873 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux",
876 24, 1, /* mux */
877 BIT(31), /* gate */
880 static SUNXI_CCU_GATE_HWS(bus_display0_top_clk, "bus-display0-top", ahb_hws,
881 0xabc, BIT(0), 0);
882 static SUNXI_CCU_GATE_HWS(bus_display1_top_clk, "bus-display1-top", ahb_hws,
883 0xacc, BIT(0), 0);
885 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0);
887 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
889 0xb10, BIT(30), 36621, 0);
895 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents,
897 24, 1, /* mux */
898 BIT(31), /* gate */
901 static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", ahb_hws, 0xb1c, BIT(0), 0);
908 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi0_clk, "mipi-dsi0",
911 24, 3, /* mux */
912 BIT(31), /* gate */
915 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi1_clk, "mipi-dsi1",
918 24, 3, /* mux */
919 BIT(31), /* gate */
922 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi0_clk, "bus-mipi-dsi0", ahb_hws, 0xb4c,
923 BIT(0), 0);
925 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi1_clk, "bus-mipi-dsi1", ahb_hws, 0xb4c,
926 BIT(1), 0);
937 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
940 24, 3, /* mux */
941 BIT(31), /* gate */
944 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
947 24, 3, /* mux */
948 BIT(31), /* gate */
958 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2",
961 24, 3, /* mux */
962 BIT(31), /* gate */
965 static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi0_clk, "combophy-dsi0",
968 24, 3, /* mux */
969 BIT(31), /* gate */
972 static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi1_clk, "combophy-dsi1",
975 24, 3, /* mux */
976 BIT(31), /* gate */
979 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0xb7c,
980 BIT(0), 0);
981 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0xb7c,
982 BIT(1), 0);
983 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0xb7c,
984 BIT(2), 0);
986 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_tv_parents,
989 24, 3, /* mux */
990 BIT(31), /* gate */
993 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_tv_parents,
996 24, 3, /* mux */
997 BIT(31), /* gate */
1000 static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0xb9c,
1001 BIT(0), 0);
1002 static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0xb9c,
1003 BIT(1), 0);
1014 24, 3, /* mux */
1015 BIT(31), /* gate */
1018 static SUNXI_CCU_GATE_HWS(bus_edp_clk, "bus-edp", ahb_hws, 0xbbc, BIT(0), 0);
1023 24, 1, /* mux */
1024 BIT(31), /* gate */
1027 static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0xbfc, BIT(0), 0);
1036 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents,
1039 24, 3, /* mux */
1040 BIT(31), /* gate */
1050 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents,
1054 24, 3, /* mux */
1055 BIT(31), /* gate */
1058 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents,
1062 24, 3, /* mux */
1063 BIT(31), /* gate */
1066 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents,
1070 24, 3, /* mux */
1071 BIT(31), /* gate */
1074 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk3_clk, "csi-mclk3", csi_mclk_parents,
1078 24, 3, /* mux */
1079 BIT(31), /* gate */
1082 static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0xc1c, BIT(0), 0);
1092 24, 3, /* mux */
1093 BIT(31), /* gate */
1105 24, 3, /* mux */
1106 BIT(31), /* gate */
1109 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
1110 0xf30, BIT(0), 0);
1111 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
1112 0xf30, BIT(1), 2, 0);
1113 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M",
1115 0xf30, BIT(2), 30, 0);
1116 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M",
1118 0xf30, BIT(3), 48, 0);
1119 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M",
1121 0xf30, BIT(4), 24, 0);
1129 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M",
1133 24, 2, /* mux */
1134 BIT(31), /* gate */
1140 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk",
1146 BIT(31), /* gate */
1150 { .fw_name = "losc-fanout" },
1162 BIT(21), /* gate */
1167 BIT(22), /* gate */
1172 BIT(23), /* gate */
1530 [RST_MBUS] = { 0x540, BIT(30) },
1531 [RST_BUS_NSI] = { 0x54c, BIT(16) },
1532 [RST_BUS_DE] = { 0x60c, BIT(16) },
1533 [RST_BUS_DI] = { 0x62c, BIT(16) },
1534 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1535 [RST_BUS_SYS] = { 0x64c, BIT(16) },
1536 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1537 [RST_BUS_CE] = { 0x68c, BIT(16) },
1538 [RST_BUS_SYS_CE] = { 0x68c, BIT(17) },
1539 [RST_BUS_VE] = { 0x69c, BIT(16) },
1540 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1541 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1542 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1543 [RST_BUS_CPUXTIMER] = { 0x74c, BIT(16) },
1544 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1545 [RST_BUS_PWM0] = { 0x7ac, BIT(16) },
1546 [RST_BUS_PWM1] = { 0x7ac, BIT(17) },
1547 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1548 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1549 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1550 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1551 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1552 [RST_BUS_SYSDAP] = { 0x88c, BIT(16) },
1553 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1554 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1555 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1556 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1557 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1558 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1559 [RST_BUS_UART6] = { 0x90c, BIT(22) },
1560 [RST_BUS_UART7] = { 0x90c, BIT(23) },
1561 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1562 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1563 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1564 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1565 [RST_BUS_I2C4] = { 0x91c, BIT(20) },
1566 [RST_BUS_I2C5] = { 0x91c, BIT(21) },
1567 [RST_BUS_CAN] = { 0x92c, BIT(16) },
1568 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1569 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1570 [RST_BUS_SPI2] = { 0x96c, BIT(18) },
1571 [RST_BUS_SPIFC] = { 0x96c, BIT(19) },
1572 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1573 [RST_BUS_EMAC1] = { 0x98c, BIT(16) | BIT(17) }, /* GMAC1-AXI */
1574 [RST_BUS_IR_RX] = { 0x99c, BIT(16) },
1575 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1576 [RST_BUS_GPADC0] = { 0x9ec, BIT(16) },
1577 [RST_BUS_GPADC1] = { 0x9ec, BIT(17) },
1578 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1579 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1580 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1581 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1582 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1583 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1584 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1585 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1586 [RST_BUS_3] = { 0xa8c, BIT(25) }, /* BSP + register */
1587 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1588 [RST_BUS_PCIE_USB3] = { 0xaac, BIT(16) },
1589 [RST_BUS_DISPLAY0_TOP] = { 0xabc, BIT(16) },
1590 [RST_BUS_DISPLAY1_TOP] = { 0xacc, BIT(16) },
1591 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1592 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1593 [RST_BUS_MIPI_DSI0] = { 0xb4c, BIT(16) },
1594 [RST_BUS_MIPI_DSI1] = { 0xb4c, BIT(17) },
1595 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1596 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
1597 [RST_BUS_TCON_LCD2] = { 0xb7c, BIT(18) },
1598 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1599 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1600 [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1601 [RST_BUS_LVDS1] = { 0xbac, BIT(17) },
1602 [RST_BUS_EDP] = { 0xbbc, BIT(16) },
1603 [RST_BUS_VIDEO_OUT0] = { 0xbcc, BIT(16) },
1604 [RST_BUS_VIDEO_OUT1] = { 0xbcc, BIT(17) },
1605 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1606 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1607 [RST_BUS_ISP] = { 0xc2c, BIT(16) }, /* BSP + register */
1646 * not support a separate enable and gate bit. We present the in sun55i_a523_ccu_probe()
1647 * gate bit(27) as the enable bit, but then have to set the in sun55i_a523_ccu_probe()
1652 val |= BIT(31) | BIT(30) | BIT(29); in sun55i_a523_ccu_probe()
1658 val &= ~(BIT(1) | BIT(0)); in sun55i_a523_ccu_probe()
1661 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_ccu_desc); in sun55i_a523_ccu_probe()
1669 { .compatible = "allwinner,sun55i-a523-ccu" },
1676 .name = "sun55i-a523-ccu",