Lines Matching +full:0 +full:x19c
29 r_ahb_apb_parents, 0x000,
30 0, 5, /* M */
32 0);
35 r_ahb_apb_parents, 0x00c,
36 0, 5, /* M */
38 0);
41 r_ahb_apb_parents, 0x010,
42 0, 5, /* M */
44 0);
47 r_ahb_apb_parents, 0x100,
48 0, 0, /* no M */
51 BIT(0),
52 0);
54 r_ahb_apb_parents, 0x104,
55 0, 0, /* no M */
58 BIT(0),
59 0);
61 r_ahb_apb_parents, 0x108,
62 0, 0, /* no M */
65 BIT(0),
66 0);
69 0x11c, BIT(0), 0);
71 0x12c, BIT(0), 0);
79 r_pwmctrl_parents, 0x130,
82 0);
84 &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
88 &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
90 &r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
92 &r_ahb_clk.common.hw, 0x17c, BIT(0), 0);
94 &r_apb1_clk.common.hw, 0x18c, BIT(0), 0);
96 &r_apb1_clk.common.hw, 0x18c, BIT(1), 0);
98 &r_apb1_clk.common.hw, 0x19c, BIT(0), 0);
100 &r_apb1_clk.common.hw, 0x19c, BIT(1), 0);
102 &r_apb1_clk.common.hw, 0x19c, BIT(2), 0);
104 &r_apb0_clk.common.hw, 0x1ac, BIT(0), 0);
106 &r_apb0_clk.common.hw, 0x1ac, BIT(1), 0);
108 &r_apb0_clk.common.hw, 0x1bc, BIT(0), 0);
115 r_ir_rx_parents, 0x1c0,
116 0, 5, /* M */
119 0);
121 &r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
124 &r_apb0_clk.common.hw, 0x1dc, BIT(0), 0);
126 &r_apb0_clk.common.hw, 0x20c, BIT(0), 0);
128 &r_apb0_clk.common.hw, 0x22c, BIT(0), 0);
192 [RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
193 [RST_BUS_R_TWD] = { 0x12c, BIT(16) },
194 [RST_BUS_R_PWMCTRL] = { 0x13c, BIT(16) },
195 [RST_BUS_R_SPI] = { 0x15c, BIT(16) },
196 [RST_BUS_R_SPINLOCK] = { 0x16c, BIT(16) },
197 [RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },
198 [RST_BUS_R_UART0] = { 0x18c, BIT(16) },
199 [RST_BUS_R_UART1] = { 0x18c, BIT(17) },
200 [RST_BUS_R_I2C0] = { 0x19c, BIT(16) },
201 [RST_BUS_R_I2C1] = { 0x19c, BIT(17) },
202 [RST_BUS_R_I2C2] = { 0x19c, BIT(18) },
203 [RST_BUS_R_PPU1] = { 0x1ac, BIT(17) },
204 [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
205 [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
206 [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
223 reg = devm_platform_ioremap_resource(pdev, 0); in sun55i_a523_r_ccu_probe()