Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
39 .enable = BIT(31),
40 .lock = BIT(28),
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
53 .enable = BIT(31),
54 .lock = BIT(28),
60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
68 .enable = BIT(31),
69 .lock = BIT(28),
75 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
83 .enable = BIT(31),
84 .lock = BIT(28),
92 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
100 .enable = BIT(31),
101 .lock = BIT(28),
109 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
117 .enable = BIT(31),
118 .lock = BIT(28),
124 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
136 .enable = BIT(31),
137 .lock = BIT(28),
146 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
154 .enable = BIT(31),
155 .lock = BIT(28),
164 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
172 .enable = BIT(31),
173 .lock = BIT(28),
182 .hw.init = CLK_HW_INIT("pll-video2", "osc24M",
190 .enable = BIT(31),
191 .lock = BIT(28),
197 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
205 .enable = BIT(31),
206 .lock = BIT(28),
212 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
219 * Sigma-delta modulation settings table obtained from the vendor SDK driver.
221 * fixed values in the probe routine. Sigma-delta modulation allows providing a
222 * fractional-N divider in the PLL, to help reaching those specific
232 .enable = BIT(31),
233 .lock = BIT(28),
237 BIT(24), 0x178, BIT(31)),
243 .hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M",
250 "iosc", "pll-cpux", "pll-periph0" };
252 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
254 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
257 "iosc", "pll-periph0" };
258 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
263 24, 2, /* mux */
267 "psi-ahb1-ahb2",
268 "pll-periph0" };
272 24, 2, /* mux */
278 24, 2, /* mux */
284 24, 2, /* mux */
287 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
288 "pll-ddr0", "pll-ddr1" };
291 24, 2, /* mux */
292 BIT(31), /* gate */
295 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
298 24, 1, /* mux */
299 BIT(31), /* gate */
302 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
303 0x60c, BIT(0), 0);
309 24, 1, /* mux */
310 BIT(31), /* gate */
313 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
314 0x62c, BIT(0), 0);
318 24, 1, /* mux */
319 BIT(31), /* gate */
322 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
323 0x63c, BIT(0), 0);
325 static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" };
328 24, 1, /* mux */
329 BIT(31), /* gate */
337 static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674,
339 BIT(31),/* gate */
342 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
343 0x67c, BIT(0), 0);
345 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
349 24, 1, /* mux */
350 BIT(31),/* gate */
353 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
354 0x68c, BIT(0), 0);
356 static const char * const ve_parents[] = { "pll-ve" };
359 24, 1, /* mux */
360 BIT(31), /* gate */
363 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
364 0x69c, BIT(0), 0);
366 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
367 0x70c, BIT(0), 0);
369 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
370 0x73c, BIT(0), 0);
372 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
374 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
375 0x78c, BIT(0), 0);
377 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
378 0x79c, BIT(0), 0);
380 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
382 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
384 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
387 .mux = _SUNXI_CCU_MUX(24, 2),
397 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
398 0x804, BIT(0), 0);
399 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
400 0x804, BIT(1), 0);
401 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
402 0x804, BIT(2), 0);
403 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
404 0x804, BIT(3), 0);
405 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
406 0x804, BIT(5), 0);
407 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
408 0x804, BIT(10), 0);
410 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
411 0x80c, BIT(0), CLK_IS_CRITICAL);
413 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
414 "pll-periph1", "pll-periph0-2x",
415 "pll-periph1-2x" };
419 24, 3, /* mux */
420 BIT(31),/* gate */
426 24, 3, /* mux */
427 BIT(31),/* gate */
430 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
432 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
433 "pll-periph1-2x" };
437 24, 2, /* mux */
438 BIT(31), /* gate */
439 2, /* post-div */
445 24, 2, /* mux */
446 BIT(31), /* gate */
447 2, /* post-div */
453 24, 2, /* mux */
454 BIT(31), /* gate */
455 2, /* post-div */
458 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
459 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
460 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
462 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
463 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
464 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
465 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
466 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
467 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
469 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
470 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
471 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
472 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
473 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0);
478 24, 3, /* mux */
479 BIT(31),/* gate */
485 24, 3, /* mux */
486 BIT(31),/* gate */
489 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
490 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
492 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
493 BIT(31) | BIT(30), 0);
495 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
496 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
498 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
502 24, 1, /* mux */
503 BIT(31),/* gate */
506 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
508 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
510 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
512 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
513 "pll-audio-4x", "pll-audio-hs" };
515 .enable = BIT(31),
517 .mux = _SUNXI_CCU_MUX(24, 2),
527 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
530 .enable = BIT(31),
532 .mux = _SUNXI_CCU_MUX(24, 2),
542 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
544 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x",
547 24, 2, /* mux */
548 BIT(31), /* gate */
550 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
553 24, 2, /* mux */
554 BIT(31), /* gate */
557 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
558 BIT(0), 0);
561 .enable = BIT(31),
563 .mux = _SUNXI_CCU_MUX(24, 2),
566 .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
573 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
584 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
585 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
587 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
588 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
590 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0);
591 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0);
593 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
594 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0);
596 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
597 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
598 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0);
599 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
600 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
601 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
602 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0);
603 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
604 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
606 static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0);
608 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x",
609 "pll-video2", "pll-video2-4x" };
612 24, 2, /* mux */
613 BIT(31), /* gate */
616 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
618 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
625 .enable = BIT(31) | BIT(30),
628 .shift = 24,
638 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
645 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
647 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
648 0xb5c, BIT(0), 0);
650 static const char * const tcon_tv_parents[] = { "pll-video0",
651 "pll-video0-4x",
652 "pll-video1",
653 "pll-video1-4x" };
654 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
656 24, 3, /* mux */
657 BIT(31), /* gate */
659 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1",
661 24, 3, /* mux */
662 BIT(31), /* gate */
664 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
665 0xb7c, BIT(0), 0);
666 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb3",
667 0xb7c, BIT(1), 0);
668 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
672 24, 3, /* mux */
673 BIT(31), /* gate */
675 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1",
679 24, 3, /* mux */
680 BIT(31), /* gate */
683 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
684 0xb9c, BIT(0), 0);
685 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3",
686 0xb9c, BIT(1), 0);
692 24, 3, /* mux */
693 BIT(31), /* gate */
696 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
697 0xbbc, BIT(0), 0);
698 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3",
699 0xbbc, BIT(1), 0);
701 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
704 24, 2, /* mux */
705 BIT(31), /* gate */
708 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
723 static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
726 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
729 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
737 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
745 static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k",
752 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
756 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
759 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
762 static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x",
1034 [RST_MBUS] = { 0x540, BIT(30) },
1036 [RST_BUS_DE] = { 0x60c, BIT(16) },
1037 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
1038 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1039 [RST_BUS_CE] = { 0x68c, BIT(16) },
1040 [RST_BUS_VE] = { 0x69c, BIT(16) },
1041 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1042 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1043 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1044 [RST_BUS_PSI] = { 0x79c, BIT(16) },
1045 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1046 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
1047 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1048 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1049 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1050 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1051 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1052 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1053 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1054 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1055 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1056 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1057 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1058 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1059 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1060 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1061 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1062 [RST_BUS_I2C4] = { 0x91c, BIT(20) },
1063 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1064 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1065 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1066 [RST_BUS_EMAC1] = { 0x97c, BIT(17) },
1067 [RST_BUS_TS] = { 0x9bc, BIT(16) },
1068 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1069 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1070 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1071 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1072 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
1073 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
1075 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1076 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1077 [RST_USB_PHY2] = { 0xa78, BIT(30) },
1078 [RST_USB_PHY3] = { 0xa7c, BIT(30) },
1079 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1080 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1081 [RST_BUS_OHCI2] = { 0xa8c, BIT(18) },
1082 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
1083 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1084 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1085 [RST_BUS_EHCI2] = { 0xa8c, BIT(22) },
1086 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
1087 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1088 [RST_BUS_KEYADC] = { 0xa9c, BIT(16) },
1090 [RST_BUS_HDMI] = { 0xb1c, BIT(16) },
1091 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1092 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
1093 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1094 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
1095 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1096 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1097 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1098 [RST_BUS_TVE0] = { 0xbbc, BIT(17) },
1099 [RST_BUS_HDCP] = { 0xc4c, BIT(16) },
1149 .enable = BIT(29), /* LOCK_ENABLE */
1150 .lock = BIT(28),
1162 .enable = BIT(29), /* LOCK_ENABLE */
1163 .lock = BIT(28),
1179 val |= BIT(29) | BIT(27); in sun50i_h616_ccu_probe()
1186 * See the comment before pll-video0 definition for the reason. in sun50i_h616_ccu_probe()
1190 val &= ~BIT(0); in sun50i_h616_ccu_probe()
1202 val &= ~GENMASK(25, 24); in sun50i_h616_ccu_probe()
1207 * Set the output-divider for the pll-audio clocks (M0) to 2 and the in sun50i_h616_ccu_probe()
1212 val &= ~BIT(1); in sun50i_h616_ccu_probe()
1213 val |= BIT(0); in sun50i_h616_ccu_probe()
1217 * Set the input-divider for the gpu1 clock to 3, to reach a safe 400 MHz. in sun50i_h616_ccu_probe()
1230 val |= BIT(24); in sun50i_h616_ccu_probe()
1233 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc); in sun50i_h616_ccu_probe()
1241 /* Re-lock the CPU PLL after any rate changes */ in sun50i_h616_ccu_probe()
1248 /* Re-lock the GPU PLL after any rate changes */ in sun50i_h616_ccu_probe()
1255 { .compatible = "allwinner,sun50i-h616-ccu" },
1263 .name = "sun50i-h616-ccu",