clk/sunxi-ng/ccu-sun20i-d1.c

55 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
70 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
106 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
130 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
154 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
165  * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
168  * The M factor must be an even number to produce a 50% duty cycle output.
172 	{ .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
179 	.m		= _SUNXI_CCU_DIV(16, 6),
180 	.sdm		= _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
210 	.m		= _SUNXI_CCU_DIV(1, 1),
243 			  0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
258 				  0, 2,		/* M */
260 				  24, 2,	/* mux */
270 				  0, 5,		/* M */
272 				  24, 2,	/* mux */
276 				  0, 5,		/* M */
278 				  24, 2,	/* mux */
292 				    0, 5,	/* M */
293 				    24, 3,	/* mux */
301 				    0, 5,	/* M */
302 				    24, 3,	/* mux */
310 				    0, 5,	/* M */
311 				    24, 3,	/* mux */
324 				       0, 4,	/* M */
326 				       24, 3,	/* mux */
338 				    0, 5,	/* M */
339 				    24, 1,	/* mux */
381 				     0, 2,	/* M */
383 				     24, 2,	/* mux */
417 					       0, 4,		/* M */
419 					       24, 3,		/* mux */
426 					       0, 4,		/* M */
428 					       24, 3,		/* mux */
442 					       0, 4,		/* M */
444 					       24, 3,		/* mux */
491 				       0, 4,	/* M */
493 				       24, 3,	/* mux */
498 				       0, 4,	/* M */
500 				       24, 3,	/* mux */
509 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
510 				      0x970, BIT(31) | BIT(30), 24, 0);
520 				       0, 4,	/* M */
522 				       24, 3,	/* mux */
542 				     0, 5,	/* M */
544 				     24, 3,	/* mux */
549 				     0, 5,	/* M */
551 				     24, 3,	/* mux */
556 				     0, 5,	/* M */
558 				     24, 3,	/* mux */
569 				     0, 5,	/* M */
571 				     24, 3,	/* mux */
583 				     0, 5,	/* M */
585 				     24, 3,	/* mux */
595 				     0, 5,	/* M */
597 				     24, 3,	/* mux */
610 				     0, 5,	/* M */
612 				     24, 3,	/* mux */
620 				     0, 5,	/* M */
622 				     24, 3,	/* mux */
627 				     0, 5,	/* M */
629 				     24, 3,	/* mux */
655 		.shift		= 24,
673 		.shift		= 24,
705 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
717 				    24, 1,	/* mux */
732 				      0, 4,	/* M */
733 				      24, 3,	/* mux */
749 				     0, 4,	/* M */
751 				     24, 3,	/* mux */
759 				     0, 4,	/* M */
761 				     24, 3,	/* mux */
769 				     0, 4,	/* M */
771 				     24, 3,	/* mux */
787 				      0, 5,	/* M */
788 				      24, 3,	/* mux */
798 				       0, 4,	/* M */
800 				       24, 1,	/* mux */
813 				    0, 4,	/* M */
814 				    24, 3,	/* mux */
827 				      0, 5,	/* M */
828 				      24, 3,	/* mux */
840 				    24, 3,	/* mux */
858 				      0, 5,	/* M */
859 				      24, 3,	/* mux */
880 				 0, 5,	/* M */
881 				 24, 3,	/* mux */
897 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
899 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
901 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
903 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
904 				      0xf30, BIT(3), 24, 0);
914 static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
915 				    0, 5,	/* M */
916 				    24, 2,	/* mux */
921 				 0, 5,		/* M */
1290 	[RST_BUS_OTG]		= { 0xa8c, BIT(24) },
1362 	/* Force PLL_CPUX factor M to 0. */  in sun20i_d1_ccu_probe()
1383 	/* Force fanout-27M factor N to 0. */  in sun20i_d1_ccu_probe()