clk/socfpga/clk-gate-a10.c

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
27 	if (socfpgaclk->fixed_div)  in socfpga_gate_clk_recalc_rate()
28 		div = socfpgaclk->fixed_div;  in socfpga_gate_clk_recalc_rate()
29 	else if (socfpgaclk->div_reg) {  in socfpga_gate_clk_recalc_rate()
30 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;  in socfpga_gate_clk_recalc_rate()
31 		val &= GENMASK(socfpgaclk->width - 1, 0);  in socfpga_gate_clk_recalc_rate()
50 	const char *clk_name = node->name;  in __socfpga_gate_init()
59 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);  in __socfpga_gate_init()
64 		socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];  in __socfpga_gate_init()
65 		socfpga_clk->hw.bit_idx = clk_gate[1];  in __socfpga_gate_init()
71 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);  in __socfpga_gate_init()
73 		socfpga_clk->fixed_div = 0;  in __socfpga_gate_init()
75 		socfpga_clk->fixed_div = fixed_div;  in __socfpga_gate_init()
77 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);  in __socfpga_gate_init()
79 		socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];  in __socfpga_gate_init()
80 		socfpga_clk->shift = div_reg[1];  in __socfpga_gate_init()
81 		socfpga_clk->width = div_reg[2];  in __socfpga_gate_init()
83 		socfpga_clk->div_reg = NULL;  in __socfpga_gate_init()
86 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_gate_init()
94 	socfpga_clk->hw.hw.init = &init;  in __socfpga_gate_init()
95 	hw_clk = &socfpga_clk->hw.hw;  in __socfpga_gate_init()