Lines Matching +full:0 +full:- +full:rtic +full:- +full:memory
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
20 #include "clk-exynos5-subcmu.h"
22 #define APLL_LOCK 0x0
23 #define APLL_CON0 0x100
24 #define SRC_CPU 0x200
25 #define DIV_CPU0 0x500
26 #define DIV_CPU1 0x504
27 #define GATE_BUS_CPU 0x700
28 #define GATE_SCLK_CPU 0x800
29 #define CLKOUT_CMU_CPU 0xa00
30 #define SRC_MASK_CPERI 0x4300
31 #define GATE_IP_G2D 0x8800
32 #define CPLL_LOCK 0x10020
33 #define DPLL_LOCK 0x10030
34 #define EPLL_LOCK 0x10040
35 #define RPLL_LOCK 0x10050
36 #define IPLL_LOCK 0x10060
37 #define SPLL_LOCK 0x10070
38 #define VPLL_LOCK 0x10080
39 #define MPLL_LOCK 0x10090
40 #define CPLL_CON0 0x10120
41 #define DPLL_CON0 0x10128
42 #define EPLL_CON0 0x10130
43 #define EPLL_CON1 0x10134
44 #define EPLL_CON2 0x10138
45 #define RPLL_CON0 0x10140
46 #define RPLL_CON1 0x10144
47 #define RPLL_CON2 0x10148
48 #define IPLL_CON0 0x10150
49 #define SPLL_CON0 0x10160
50 #define VPLL_CON0 0x10170
51 #define MPLL_CON0 0x10180
52 #define SRC_TOP0 0x10200
53 #define SRC_TOP1 0x10204
54 #define SRC_TOP2 0x10208
55 #define SRC_TOP3 0x1020c
56 #define SRC_TOP4 0x10210
57 #define SRC_TOP5 0x10214
58 #define SRC_TOP6 0x10218
59 #define SRC_TOP7 0x1021c
60 #define SRC_TOP8 0x10220 /* 5800 specific */
61 #define SRC_TOP9 0x10224 /* 5800 specific */
62 #define SRC_DISP10 0x1022c
63 #define SRC_MAU 0x10240
64 #define SRC_FSYS 0x10244
65 #define SRC_PERIC0 0x10250
66 #define SRC_PERIC1 0x10254
67 #define SRC_ISP 0x10270
68 #define SRC_CAM 0x10274 /* 5800 specific */
69 #define SRC_TOP10 0x10280
70 #define SRC_TOP11 0x10284
71 #define SRC_TOP12 0x10288
72 #define SRC_TOP13 0x1028c /* 5800 specific */
73 #define SRC_MASK_TOP0 0x10300
74 #define SRC_MASK_TOP1 0x10304
75 #define SRC_MASK_TOP2 0x10308
76 #define SRC_MASK_TOP7 0x1031c
77 #define SRC_MASK_DISP10 0x1032c
78 #define SRC_MASK_MAU 0x10334
79 #define SRC_MASK_FSYS 0x10340
80 #define SRC_MASK_PERIC0 0x10350
81 #define SRC_MASK_PERIC1 0x10354
82 #define SRC_MASK_ISP 0x10370
83 #define DIV_TOP0 0x10500
84 #define DIV_TOP1 0x10504
85 #define DIV_TOP2 0x10508
86 #define DIV_TOP8 0x10520 /* 5800 specific */
87 #define DIV_TOP9 0x10524 /* 5800 specific */
88 #define DIV_DISP10 0x1052c
89 #define DIV_MAU 0x10544
90 #define DIV_FSYS0 0x10548
91 #define DIV_FSYS1 0x1054c
92 #define DIV_FSYS2 0x10550
93 #define DIV_PERIC0 0x10558
94 #define DIV_PERIC1 0x1055c
95 #define DIV_PERIC2 0x10560
96 #define DIV_PERIC3 0x10564
97 #define DIV_PERIC4 0x10568
98 #define DIV_CAM 0x10574 /* 5800 specific */
99 #define SCLK_DIV_ISP0 0x10580
100 #define SCLK_DIV_ISP1 0x10584
101 #define DIV2_RATIO0 0x10590
102 #define DIV4_RATIO 0x105a0
103 #define GATE_BUS_TOP 0x10700
104 #define GATE_BUS_DISP1 0x10728
105 #define GATE_BUS_GEN 0x1073c
106 #define GATE_BUS_FSYS0 0x10740
107 #define GATE_BUS_FSYS2 0x10748
108 #define GATE_BUS_PERIC 0x10750
109 #define GATE_BUS_PERIC1 0x10754
110 #define GATE_BUS_PERIS0 0x10760
111 #define GATE_BUS_PERIS1 0x10764
112 #define GATE_BUS_NOC 0x10770
113 #define GATE_TOP_SCLK_ISP 0x10870
114 #define GATE_IP_GSCL0 0x10910
115 #define GATE_IP_GSCL1 0x10920
116 #define GATE_IP_CAM 0x10924 /* 5800 specific */
117 #define GATE_IP_MFC 0x1092c
118 #define GATE_IP_DISP1 0x10928
119 #define GATE_IP_G3D 0x10930
120 #define GATE_IP_GEN 0x10934
121 #define GATE_IP_FSYS 0x10944
122 #define GATE_IP_PERIC 0x10950
123 #define GATE_IP_PERIS 0x10960
124 #define GATE_IP_MSCL 0x10970
125 #define GATE_TOP_SCLK_GSCL 0x10820
126 #define GATE_TOP_SCLK_DISP1 0x10828
127 #define GATE_TOP_SCLK_MAU 0x1083c
128 #define GATE_TOP_SCLK_FSYS 0x10840
129 #define GATE_TOP_SCLK_PERIC 0x10850
130 #define TOP_SPARE2 0x10b08
131 #define BPLL_LOCK 0x20010
132 #define BPLL_CON0 0x20110
133 #define SRC_CDREX 0x20200
134 #define DIV_CDREX0 0x20500
135 #define DIV_CDREX1 0x20504
136 #define GATE_BUS_CDREX0 0x20700
137 #define GATE_BUS_CDREX1 0x20704
138 #define KPLL_LOCK 0x28000
139 #define KPLL_CON0 0x28100
140 #define SRC_KFC 0x28200
141 #define DIV_KFC0 0x28500
279 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
280 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
281 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
282 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
283 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
284 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
285 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
286 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
287 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
288 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
289 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
290 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
291 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
292 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
293 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
449 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
454 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
455 FRATE(0, "sclk_pwi", NULL, 0, 24000000),
456 FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
457 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
458 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
463 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
464 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
469 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
470 FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
474 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
475 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
476 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
477 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
479 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
480 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
481 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
482 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
483 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
485 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
486 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
487 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
488 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
489 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
490 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
493 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
498 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
500 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
502 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
503 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
504 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
505 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
508 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
509 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
511 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
513 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
515 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
518 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
519 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
521 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
523 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
526 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
532 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
534 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
536 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
538 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
541 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
542 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
547 GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
549 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
553 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
554 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
557 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
558 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
559 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
560 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
562 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
563 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
565 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
566 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
567 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
569 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
570 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
571 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
572 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
573 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
574 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
578 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
579 CLK_SET_RATE_PARENT, 0),
581 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
590 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
593 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
595 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
597 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
601 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
607 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
608 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
609 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
610 MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
611 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
612 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
614 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
615 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
616 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
617 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
619 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
620 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
622 MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
623 CLK_SET_RATE_PARENT, 0),
625 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
626 SRC_TOP3, 0, 1),
627 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
631 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
633 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
635 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
637 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
639 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
642 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
643 SRC_TOP4, 0, 1),
644 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
646 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
648 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
650 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
652 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
653 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
658 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
659 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
661 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
663 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
666 SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
667 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
674 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
676 CLK_SET_RATE_PARENT, 0),
678 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
679 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
681 CLK_SET_RATE_PARENT, 0),
682 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
683 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
685 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
686 SRC_TOP10, 0, 1),
687 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
691 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
693 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
695 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
697 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
699 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
702 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
703 SRC_TOP11, 0, 1),
704 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
706 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
707 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
709 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
710 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
716 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
718 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
721 SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
722 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
730 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
731 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
732 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
734 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
736 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
740 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
741 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
742 CLK_SET_RATE_PARENT, 0),
748 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
749 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
750 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
751 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
752 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
753 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
754 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
757 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
758 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
759 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
760 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
761 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
762 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
763 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
764 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
765 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
766 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
767 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
768 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
771 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
772 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
773 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
774 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
775 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
779 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
780 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
781 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
782 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
783 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
786 DIV_TOP0, 0, 3),
800 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
819 16, 3, CLK_SET_RATE_PARENT, 0),
828 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
829 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
830 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
839 * synchronization between the BUS and DREXs (two external memory
845 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
847 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
849 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
852 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
864 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
865 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
867 /* USB3.0 */
868 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
869 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
870 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
871 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
874 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
875 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
876 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
878 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
879 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
882 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
883 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
884 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
885 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
886 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
889 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
890 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
891 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
895 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
896 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
898 /* Audio - I2S */
899 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
900 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
901 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
902 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
903 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
905 /* SPI Pre-Ratio */
906 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
907 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
908 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
911 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
914 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
915 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
918 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
919 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
920 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
921 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
922 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
923 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
924 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
925 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
926 CLK_SET_RATE_PARENT, 0),
927 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
928 CLK_SET_RATE_PARENT, 0),
933 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
934 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
935 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
936 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
937 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
939 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
940 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
941 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
942 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
944 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
945 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
946 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
947 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
948 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
949 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
950 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
951 GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
952 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
953 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
954 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
955 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
956 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
957 GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
959 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
960 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
961 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
962 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
963 GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
964 GATE(0, "aclk166", "mout_user_aclk166",
965 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
967 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
968 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
969 GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
970 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
971 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
972 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
973 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
975 GATE_BUS_TOP, 28, 0, 0),
977 GATE_BUS_TOP, 29, 0, 0),
979 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
980 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
984 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
986 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
988 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
990 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
992 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
994 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
996 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
998 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
1000 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1002 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
1004 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
1006 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
1008 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
1011 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
1013 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
1015 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1017 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1019 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1021 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1023 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1027 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1029 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1031 GATE_TOP_SCLK_DISP1, 9, 0, 0),
1033 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1035 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1038 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1039 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1040 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1041 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1042 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1043 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1044 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1045 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1047 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1048 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1049 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1050 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1052 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1056 GATE_IP_PERIC, 0, 0, 0),
1058 GATE_IP_PERIC, 1, 0, 0),
1060 GATE_IP_PERIC, 2, 0, 0),
1062 GATE_IP_PERIC, 3, 0, 0),
1064 GATE_IP_PERIC, 6, 0, 0),
1066 GATE_IP_PERIC, 7, 0, 0),
1068 GATE_IP_PERIC, 8, 0, 0),
1070 GATE_IP_PERIC, 9, 0, 0),
1072 GATE_IP_PERIC, 10, 0, 0),
1074 GATE_IP_PERIC, 11, 0, 0),
1076 GATE_IP_PERIC, 12, 0, 0),
1078 GATE_IP_PERIC, 13, 0, 0),
1080 GATE_IP_PERIC, 14, 0, 0),
1082 GATE_IP_PERIC, 15, 0, 0),
1084 GATE_IP_PERIC, 16, 0, 0),
1086 GATE_IP_PERIC, 17, 0, 0),
1088 GATE_IP_PERIC, 18, 0, 0),
1090 GATE_IP_PERIC, 20, 0, 0),
1092 GATE_IP_PERIC, 21, 0, 0),
1094 GATE_IP_PERIC, 22, 0, 0),
1096 GATE_IP_PERIC, 23, 0, 0),
1098 GATE_IP_PERIC, 24, 0, 0),
1100 GATE_IP_PERIC, 26, 0, 0),
1102 GATE_IP_PERIC, 28, 0, 0),
1104 GATE_IP_PERIC, 30, 0, 0),
1106 GATE_IP_PERIC, 31, 0, 0),
1109 GATE_BUS_PERIC, 22, 0, 0),
1113 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1115 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1116 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1117 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1118 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1119 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1120 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1121 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1122 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1123 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1124 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1125 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1126 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1127 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1128 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1129 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1130 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1131 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1134 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1135 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1136 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1137 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1138 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1140 GATE_IP_GEN, 6, 0, 0),
1141 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1143 GATE_IP_GEN, 9, 0, 0),
1147 GATE_BUS_GEN, 28, 0, 0),
1148 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1152 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1154 GATE_TOP_SCLK_GSCL, 7, 0, 0),
1157 GATE_IP_GSCL0, 4, 0, 0),
1159 GATE_IP_GSCL0, 5, 0, 0),
1161 GATE_IP_GSCL0, 6, 0, 0),
1164 GATE_IP_GSCL1, 2, 0, 0),
1166 GATE_IP_GSCL1, 3, 0, 0),
1168 GATE_IP_GSCL1, 4, 0, 0),
1170 CLK_IS_CRITICAL, 0),
1172 CLK_IS_CRITICAL, 0),
1174 GATE_IP_GSCL1, 16, 0, 0),
1176 GATE_IP_GSCL1, 17, 0, 0),
1180 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1182 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1184 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1186 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1188 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1190 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1192 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1196 GATE_BUS_CDREX0, 0, 0, 0),
1198 GATE_BUS_CDREX0, 1, 0, 0),
1199 GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
1200 SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
1203 GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
1205 GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
1207 GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
1209 GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
1212 GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
1214 GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
1216 GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
1218 GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
1222 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1226 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1227 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1228 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1229 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1230 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1232 GATE_IP_DISP1, 7, 0, 0),
1234 GATE_IP_DISP1, 8, 0, 0),
1236 GATE_IP_DISP1, 9, 0, 0),
1240 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1241 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
1242 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
1243 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
1244 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
1248 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1253 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1254 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1256 GATE_IP_GSCL1, 6, 0, 0),
1258 GATE_IP_GSCL1, 7, 0, 0),
1262 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
1263 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
1264 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
1265 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
1270 CLK_SET_RATE_PARENT, 0),
1274 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1275 { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
1279 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1283 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1284 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1285 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1289 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1290 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
1291 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
1296 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1297 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1298 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1300 GATE_IP_MSCL, 8, 0, 0),
1302 GATE_IP_MSCL, 9, 0, 0),
1304 GATE_IP_MSCL, 10, 0, 0),
1308 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
1312 { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
1313 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
1314 { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
1319 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
1321 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1323 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1327 { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
1404 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1409 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1410 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1411 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1437 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1438 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1439 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1441 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1442 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1445 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1449 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
1512 { 0 },
1535 { 0 },
1555 { 0 },
1559 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1560 0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d),
1561 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1562 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1566 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1567 0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d),
1568 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1569 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1573 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1585 reg_base = of_iomap(np, 0); in exynos5x_clk_init()
1595 hws = ctx->clk_data.hws; in exynos5x_clk_init()
1672 clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); in exynos5x_clk_init()
1677 clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); in exynos5x_clk_init()
1686 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1693 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",