Lines Matching +full:11 +full:- +full:7
1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
29 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
42 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
43 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
44 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
45 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
48 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
49 RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
50 RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
51 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
52 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
70 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
74 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
78 RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
79 RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
80 RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
81 RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
82 RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
83 RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
84 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
85 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
86 RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
87 RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
88 RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
98 RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
102 RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
115 RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
119 RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
143 RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
156 RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
160 RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
166 RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
170 RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
183 RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
186 RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
199 RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
201 RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
248 RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
251 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
275 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
300 RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
302 RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
310 RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
314 RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
326 RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
332 RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
343 RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
354 RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
365 RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
368 RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
394 RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
396 RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
410 RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
412 RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
427 RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
430 RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
437 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
452 RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
465 RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
475 RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
499 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
512 RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
519 RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
529 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
533 RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
557 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
578 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
582 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
594 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
598 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
609 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
619 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
622 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
638 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
639 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
640 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
641 RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),