clk/rockchip/rst-rk3528.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
9 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
280 	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
281 	RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
282 	RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
283 	RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
284 	RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
285 	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
286 	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
287 	RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
288 	RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
289 	RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
290 	RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
291 	RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
292 	RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
293 	RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),