clk/rockchip/rst-rk3528.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
26 	RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
27 	RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
42 	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
43 	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
44 	RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
45 	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
46 	RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
47 	RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
48 	RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
49 	RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
52 	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
53 	RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
54 	RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
55 	RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
56 	RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
57 	RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
58 	RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
59 	RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
60 	RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
61 	RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
62 	RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
63 	RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
64 	RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
65 	RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
71 	RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
82 	RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
90 	RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
91 	RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
107 	RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
108 	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
120 	RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
121 	RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
150 	RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
151 	RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
165 	RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
166 	RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
174 	RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
175 	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
185 	RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
186 	RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
200 	RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
201 	RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
209 	RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
210 	RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
237 	RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
249 	RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
260 	RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
261 	RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
274 	RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
275 	RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
286 	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
287 	RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),