clk/rockchip/rst-rk3528.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
28 	RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
45 	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
46 	RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
61 	RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
62 	RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
68 	RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
69 	RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
70 	RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
71 	RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
72 	RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
73 	RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
74 	RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
75 	RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
76 	RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
79 	RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
80 	RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
81 	RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
82 	RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
83 	RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
84 	RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
85 	RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
92 	RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
93 	RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
109 	RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
110 	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
122 	RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
123 	RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
152 	RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
153 	RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
176 	RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
177 	RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
187 	RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
202 	RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
211 	RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
212 	RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
238 	RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
250 	RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
262 	RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
263 	RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
276 	RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
288 	RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
289 	RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),