Lines Matching full:gate
263 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
265 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
267 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
269 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
271 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
276 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
278 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
280 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
282 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
284 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
289 GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0,
291 GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0,
293 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
295 GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
297 GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
299 GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
301 GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
303 GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
305 GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
307 GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED,
309 GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED,
311 GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED,
313 GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0,
315 GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0,
317 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED,
319 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED,
321 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
323 GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0,
325 GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED,
327 GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0,
329 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED,
331 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED,
333 GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0,
335 GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0,
337 GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED,
339 GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED,
341 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
349 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED,
354 GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0,
356 GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0,
367 GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL,
369 GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL,
371 GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0,
373 GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0,
375 GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED,
377 GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0,
379 GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED,
381 GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL,
383 GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL,
385 GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0,
387 GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0,
389 GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0,
391 GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0,
393 GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0,
409 GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
421 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED,
423 GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED,
425 GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED,
427 GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED,
429 GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED,
431 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
433 GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
435 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
437 GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED,
439 GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED,
449 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0,
462 GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0,
464 GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0,
477 GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED,
479 GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0,
488 GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0,
493 GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0,
502 GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0,
507 GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0,
516 GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0,
521 GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0,
523 GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0,
525 GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0,
530 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0,
539 GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0,
541 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0,
548 GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0,
555 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0,
557 GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0,
565 GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
570 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0,
572 GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0,
574 GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0,
576 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0,
581 GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
583 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0,
588 GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0,
590 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0,
592 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0,
594 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0,
596 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0,
598 GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0,
600 GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0,
602 GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0,
604 GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0,
606 GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0,
615 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
624 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
633 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
642 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
651 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
660 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
669 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
678 GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
687 GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
689 GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0,
694 GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
696 GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0,
701 GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
703 GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0,
708 GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0,
710 GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0,
715 GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0,
720 GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0,
725 GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED,
727 GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED,
729 GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED,
731 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0,
733 GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0,
735 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0,
737 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
742 GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED,
744 GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
749 GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
751 GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0,
753 GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0,
755 GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0,
757 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0,
762 GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL,
764 GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0,
766 GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0,
771 GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0,
773 GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0,
783 GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0,
785 GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0,
787 GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0,
789 GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0,
791 GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0,
793 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0,
798 GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
800 GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0,
815 GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
817 GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
819 GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED,
821 GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
823 GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED,
825 GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED,
827 GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0,
829 GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0,
831 GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL,
833 GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0,
835 GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0,
837 GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
839 GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
841 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
843 GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
848 GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0,
853 GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0,
858 GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0,
863 GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0,
869 GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
871 GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
873 GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0,
882 GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0,
884 GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0,
889 GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0,
891 GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0,
896 GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0,
898 GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0,
900 GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0,
902 GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0,
904 GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0,
906 GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0,
908 GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0,
918 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0,
920 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
925 GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0,
927 GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
940 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0,
942 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0,
955 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0,
957 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0,
970 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0,
972 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
977 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0,
979 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
984 GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0,
986 GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0,
988 GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0,
990 GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0,
992 GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0,
994 GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0,
996 GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0,
998 GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0,
1000 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0,
1002 GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0,
1012 GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0,
1014 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0,