Lines Matching full:7
96 PX30_CPUCLK_RATE(1608000000, 1, 7),
97 PX30_CPUCLK_RATE(1584000000, 1, 7),
98 PX30_CPUCLK_RATE(1560000000, 1, 7),
99 PX30_CPUCLK_RATE(1536000000, 1, 7),
100 PX30_CPUCLK_RATE(1512000000, 1, 7),
133 .mux_core_shift = 7,
333 PX30_CLKGATE_CON(0), 7, GFLAGS),
337 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
339 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
369 PX30_CLKGATE_CON(1), 7, GFLAGS),
420 PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
436 PX30_CLKGATE_CON(2), 7, GFLAGS,
453 * Clock-Architecture Diagram 7
458 PX30_CLKGATE_CON(5), 7, GFLAGS),
505 PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
506 PX30_CLKGATE_CON(6), 7, GFLAGS),
540 PX30_CLKGATE_CON(7), 2, GFLAGS),
542 PX30_CLKGATE_CON(7), 3, GFLAGS),
547 PX30_CLKGATE_CON(7), 11, GFLAGS),
551 PX30_CLKGATE_CON(7), 15, GFLAGS),
553 PX30_CLKGATE_CON(7), 13, GFLAGS),
557 PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
560 PX30_CLKGATE_CON(7), 10, GFLAGS),
563 PX30_CLKGATE_CON(7), 12, GFLAGS),
582 PX30_CLKGATE_CON(8), 7, GFLAGS),
590 PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
600 PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
616 PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
632 PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
647 PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
657 PX30_CLKGATE_CON(10), 7, GFLAGS),
698 PX30_CLKGATE_CON(11), 7, GFLAGS),
727 PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
730 PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
733 PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
736 PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
739 PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
742 PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
745 PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
746 PX30_CLKGATE_CON(12), 7, GFLAGS),
748 PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
804 GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
817 GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
848 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
864 …GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAG…
872 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
884 GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
885 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
898 GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS),
899 GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
900 GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
901 …GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS…
962 PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
976 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),