51 			    struct rockchip_clk_pll *pll, unsigned long rate)  in rockchip_get_pll_settings()  argument
53 	const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;  in rockchip_get_pll_settings()
56 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_get_pll_settings()
67 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_pll_round_rate()  local
68 	const struct rockchip_pll_rate_table *rate_table = pll->rate_table;  in rockchip_pll_round_rate()
72 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_pll_round_rate()
82  * Wait for the pll to reach the locked state.
86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_pll_wait_lock()  argument
88 	struct regmap *grf = pll->ctx->grf;  in rockchip_pll_wait_lock()
92 	ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,  in rockchip_pll_wait_lock()
93 				       val & BIT(pll->lock_shift), 0, 1000);  in rockchip_pll_wait_lock()
95 		pr_err("%s: timeout waiting for pll to lock\n", __func__);  in rockchip_pll_wait_lock()
101  * PLL used in RK3036
120 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_rk3036_pll_wait_lock()  argument
129 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),  in rockchip_rk3036_pll_wait_lock()
134 		pr_err("%s: timeout waiting for pll to lock\n", __func__);  in rockchip_rk3036_pll_wait_lock()
139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3036_pll_get_params()  argument
144 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));  in rockchip_rk3036_pll_get_params()
150 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_get_params()
158 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_get_params()
166 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_recalc_rate()  local
170 	rockchip_rk3036_pll_get_params(pll, &cur);  in rockchip_rk3036_pll_recalc_rate()
189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3036_pll_set_params()  argument
192 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3036_pll_set_params()
193 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3036_pll_set_params()
204 	rockchip_rk3036_pll_get_params(pll, &cur);  in rockchip_rk3036_pll_set_params()
207 	if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {  in rockchip_rk3036_pll_set_params()
215 	/* update pll values */  in rockchip_rk3036_pll_set_params()
220 		       pll->reg_base + RK3036_PLLCON(0));  in rockchip_rk3036_pll_set_params()
228 		       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_set_params()
231 	pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_set_params()
234 	writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));  in rockchip_rk3036_pll_set_params()
236 	/* wait for the pll to lock */  in rockchip_rk3036_pll_set_params()
237 	ret = rockchip_rk3036_pll_wait_lock(pll);  in rockchip_rk3036_pll_set_params()
239 		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",  in rockchip_rk3036_pll_set_params()
241 		rockchip_rk3036_pll_set_params(pll, &cur);  in rockchip_rk3036_pll_set_params()
253 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_set_rate()  local
260 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3036_pll_set_rate()
262 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in rockchip_rk3036_pll_set_rate()
267 	return rockchip_rk3036_pll_set_params(pll, rate);  in rockchip_rk3036_pll_set_rate()
272 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_enable()  local
275 	       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_enable()
276 	rockchip_rk3036_pll_wait_lock(pll);  in rockchip_rk3036_pll_enable()
283 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_disable()  local
287 	       pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_disable()
292 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_is_enabled()  local
293 	u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));  in rockchip_rk3036_pll_is_enabled()
300 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3036_pll_init()  local
305 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3036_pll_init()
309 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3036_pll_init()
315 	rockchip_rk3036_pll_get_params(pll, &cur);  in rockchip_rk3036_pll_init()
317 	pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),  in rockchip_rk3036_pll_init()
338 		pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",  in rockchip_rk3036_pll_init()
340 		rockchip_rk3036_pll_set_params(pll, rate);  in rockchip_rk3036_pll_init()
364  * PLL used in RK3066, RK3188 and RK3288
382 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3066_pll_get_params()  argument
387 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_get_params()
393 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_get_params()
397 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_get_params()
405 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_recalc_rate()  local
410 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_recalc_rate()
412 		pr_debug("%s: pll %s is bypassed\n", __func__,  in rockchip_rk3066_pll_recalc_rate()
417 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_recalc_rate()
426 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3066_pll_set_params()  argument
429 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3066_pll_set_params()
430 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_params()
439 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_set_params()
450 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_params()
452 	/* update pll values */  in rockchip_rk3066_pll_set_params()
457 	       pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_set_params()
461 		       pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_set_params()
464 		       pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_set_params()
468 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_params()
471 	/* wait for the pll to lock */  in rockchip_rk3066_pll_set_params()
472 	ret = rockchip_pll_wait_lock(pll);  in rockchip_rk3066_pll_set_params()
474 		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",  in rockchip_rk3066_pll_set_params()
476 		rockchip_rk3066_pll_set_params(pll, &cur);  in rockchip_rk3066_pll_set_params()
488 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_set_rate()  local
495 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_set_rate()
497 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in rockchip_rk3066_pll_set_rate()
502 	return rockchip_rk3066_pll_set_params(pll, rate);  in rockchip_rk3066_pll_set_rate()
507 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_enable()  local
510 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_enable()
511 	rockchip_pll_wait_lock(pll);  in rockchip_rk3066_pll_enable()
518 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_disable()  local
522 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_disable()
527 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_is_enabled()  local
528 	u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_is_enabled()
535 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_init()  local
540 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3066_pll_init()
544 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_init()
550 	rockchip_rk3066_pll_get_params(pll, &cur);  in rockchip_rk3066_pll_init()
552 	pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",  in rockchip_rk3066_pll_init()
557 		pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",  in rockchip_rk3066_pll_init()
559 		rockchip_rk3066_pll_set_params(pll, rate);  in rockchip_rk3066_pll_init()
583  * PLL used in RK3399
602 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_rk3399_pll_wait_lock()  argument
611 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),  in rockchip_rk3399_pll_wait_lock()
616 		pr_err("%s: timeout waiting for pll to lock\n", __func__);  in rockchip_rk3399_pll_wait_lock()
621 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3399_pll_get_params()  argument
626 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_get_params()
630 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_get_params()
638 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_get_params()
642 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_get_params()
650 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_recalc_rate()  local
654 	rockchip_rk3399_pll_get_params(pll, &cur);  in rockchip_rk3399_pll_recalc_rate()
673 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3399_pll_set_params()  argument
676 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3399_pll_set_params()
677 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3399_pll_set_params()
688 	rockchip_rk3399_pll_get_params(pll, &cur);  in rockchip_rk3399_pll_set_params()
697 	/* update pll values */  in rockchip_rk3399_pll_set_params()
700 		       pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3399_pll_set_params()
708 		       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3399_pll_set_params()
711 	pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
714 	writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3399_pll_set_params()
718 		       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_set_params()
720 	/* wait for the pll to lock */  in rockchip_rk3399_pll_set_params()
721 	ret = rockchip_rk3399_pll_wait_lock(pll);  in rockchip_rk3399_pll_set_params()
723 		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",  in rockchip_rk3399_pll_set_params()
725 		rockchip_rk3399_pll_set_params(pll, &cur);  in rockchip_rk3399_pll_set_params()
737 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_set_rate()  local
744 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3399_pll_set_rate()
746 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in rockchip_rk3399_pll_set_rate()
751 	return rockchip_rk3399_pll_set_params(pll, rate);  in rockchip_rk3399_pll_set_rate()
756 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_enable()  local
759 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_enable()
760 	rockchip_rk3399_pll_wait_lock(pll);  in rockchip_rk3399_pll_enable()
767 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_disable()  local
771 	       pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_disable()
776 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_is_enabled()  local
777 	u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));  in rockchip_rk3399_pll_is_enabled()
784 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3399_pll_init()  local
789 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3399_pll_init()
793 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3399_pll_init()
799 	rockchip_rk3399_pll_get_params(pll, &cur);  in rockchip_rk3399_pll_init()
801 	pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),  in rockchip_rk3399_pll_init()
822 		pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",  in rockchip_rk3399_pll_init()
824 		rockchip_rk3399_pll_set_params(pll, rate);  in rockchip_rk3399_pll_init()
848  * PLL used in RK3588
863 static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_rk3588_pll_wait_lock()  argument
872 	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),  in rockchip_rk3588_pll_wait_lock()
877 		pr_err("%s: timeout waiting for pll to lock\n", __func__);  in rockchip_rk3588_pll_wait_lock()
882 static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,  in rockchip_rk3588_pll_get_params()  argument
887 	pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));  in rockchip_rk3588_pll_get_params()
890 	pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));  in rockchip_rk3588_pll_get_params()
894 	pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));  in rockchip_rk3588_pll_get_params()
900 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3588_pll_recalc_rate()  local
904 	rockchip_rk3588_pll_get_params(pll, &cur);  in rockchip_rk3588_pll_recalc_rate()
919 	if (pll->type == pll_rk3588_ddr)  in rockchip_rk3588_pll_recalc_rate()
925 static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,  in rockchip_rk3588_pll_set_params()  argument
928 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3588_pll_set_params()
929 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3588_pll_set_params()
938 	rockchip_rk3588_pll_get_params(pll, &cur);  in rockchip_rk3588_pll_set_params()
941 	if (pll->type == pll_rk3588) {  in rockchip_rk3588_pll_set_params()
949 	/* set pll power down */  in rockchip_rk3588_pll_set_params()
952 	       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3588_pll_set_params()
954 	/* update pll values */  in rockchip_rk3588_pll_set_params()
956 		       pll->reg_base + RK3399_PLLCON(0));  in rockchip_rk3588_pll_set_params()
960 		       pll->reg_base + RK3399_PLLCON(1));  in rockchip_rk3588_pll_set_params()
963 		       pll->reg_base + RK3399_PLLCON(2));  in rockchip_rk3588_pll_set_params()
965 	/* set pll power up */  in rockchip_rk3588_pll_set_params()
967 	       pll->reg_base + RK3588_PLLCON(1));  in rockchip_rk3588_pll_set_params()
969 	/* wait for the pll to lock */  in rockchip_rk3588_pll_set_params()
970 	ret = rockchip_rk3588_pll_wait_lock(pll);  in rockchip_rk3588_pll_set_params()
972 		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",  in rockchip_rk3588_pll_set_params()
974 		rockchip_rk3588_pll_set_params(pll, &cur);  in rockchip_rk3588_pll_set_params()
977 	if ((pll->type == pll_rk3588) && rate_change_remuxed)  in rockchip_rk3588_pll_set_params()
986 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3588_pll_set_rate()  local
993 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3588_pll_set_rate()
995 		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,  in rockchip_rk3588_pll_set_rate()
1000 	return rockchip_rk3588_pll_set_params(pll, rate);  in rockchip_rk3588_pll_set_rate()
1005 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3588_pll_enable()  local
1008 	       pll->reg_base + RK3588_PLLCON(1));  in rockchip_rk3588_pll_enable()
1009 	rockchip_rk3588_pll_wait_lock(pll);  in rockchip_rk3588_pll_enable()
1016 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3588_pll_disable()  local
1019 	       pll->reg_base + RK3588_PLLCON(1));  in rockchip_rk3588_pll_disable()
1024 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3588_pll_is_enabled()  local
1025 	u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));  in rockchip_rk3588_pll_is_enabled()
1032 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3588_pll_init()  local
1034 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3588_pll_init()
1058  * Common registering of pll clocks
1071 	struct rockchip_clk_pll *pll;  in rockchip_clk_register_pll()  local
1082 	/* name the actual pll */  in rockchip_clk_register_pll()
1085 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in rockchip_clk_register_pll()
1086 	if (!pll)  in rockchip_clk_register_pll()
1089 	/* create the mux on top of the real pll */  in rockchip_clk_register_pll()
1090 	pll->pll_mux_ops = &clk_mux_ops;  in rockchip_clk_register_pll()
1091 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
1109 	/* the actual muxing is xin24m, pll-output, xin32k */  in rockchip_clk_register_pll()
1116 	init.ops = pll->pll_mux_ops;  in rockchip_clk_register_pll()
1127 	/* now create the actual pll */  in rockchip_clk_register_pll()
1143 		pll->rate_count = len;  in rockchip_clk_register_pll()
1144 		pll->rate_table = kmemdup_array(rate_table,  in rockchip_clk_register_pll()
1145 						pll->rate_count,  in rockchip_clk_register_pll()
1146 						sizeof(*pll->rate_table),  in rockchip_clk_register_pll()
1148 		WARN(!pll->rate_table,  in rockchip_clk_register_pll()
1156 		if (!pll->rate_table)  in rockchip_clk_register_pll()
1162 		if (!pll->rate_table || IS_ERR(ctx->grf))  in rockchip_clk_register_pll()
1168 		if (!pll->rate_table)  in rockchip_clk_register_pll()
1176 		if (!pll->rate_table)  in rockchip_clk_register_pll()
1183 		pr_warn("%s: Unknown pll type for pll clk %s\n",  in rockchip_clk_register_pll()
1187 	pll->hw.init = &init;  in rockchip_clk_register_pll()
1188 	pll->type = pll_type;  in rockchip_clk_register_pll()
1189 	pll->reg_base = ctx->reg_base + con_offset;  in rockchip_clk_register_pll()
1190 	pll->lock_offset = grf_lock_offset;  in rockchip_clk_register_pll()
1191 	pll->lock_shift = lock_shift;  in rockchip_clk_register_pll()
1192 	pll->flags = clk_pll_flags;  in rockchip_clk_register_pll()
1193 	pll->lock = &ctx->lock;  in rockchip_clk_register_pll()
1194 	pll->ctx = ctx;  in rockchip_clk_register_pll()
1196 	pll_clk = clk_register(NULL, &pll->hw);  in rockchip_clk_register_pll()
1198 		pr_err("%s: failed to register pll clock %s : %ld\n",  in rockchip_clk_register_pll()
1206 	kfree(pll->rate_table);  in rockchip_clk_register_pll()
1210 	kfree(pll);  in rockchip_clk_register_pll()