Lines Matching +full:cpg +full:- +full:mstp +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
45 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
46 * R-Car Gen2, R-Car Gen3, and RZ/G1.
47 * These are NOT valid for R-Car Gen1 and RZ/A1!
125 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
129 * @dev: CPG/MSSR device
130 * @base: CPG/MSSR register block base address
131 * @reg_layout: CPG/MSSR register layout
133 * @np: Device node in DT for this CPG/MSSR module
134 * @num_core_clks: Number of Core Clocks in clks[]
135 * @num_mod_clks: Number of Module Clocks in clks[]
146 * @clks: Array containing all Core and Module Clocks
181 * struct mstp_clock - MSTP gating clock
182 * @hw: handle between common and hardware-specific interfaces
183 * @index: MSTP clock number
184 * @priv: CPG/MSSR private data
197 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_endisable()
198 unsigned int reg = clock->index / 32; in cpg_mstp_clock_endisable()
199 unsigned int bit = clock->index % 32; in cpg_mstp_clock_endisable()
200 struct device *dev = priv->dev; in cpg_mstp_clock_endisable()
206 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, in cpg_mstp_clock_endisable()
208 spin_lock_irqsave(&priv->rmw_lock, flags); in cpg_mstp_clock_endisable()
210 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
211 value = readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
216 writeb(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
219 readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
220 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
222 value = readl(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
227 writel(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()
230 spin_unlock_irqrestore(&priv->rmw_lock, flags); in cpg_mstp_clock_endisable()
232 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
235 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], in cpg_mstp_clock_endisable()
239 priv->base + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()
257 struct cpg_mssr_priv *priv = clock->priv; in cpg_mstp_clock_is_enabled()
260 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
261 value = readb(priv->base + priv->control_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()
263 value = readl(priv->base + priv->status_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()
265 return !(value & BIT(clock->index % 32)); in cpg_mstp_clock_is_enabled()
278 unsigned int clkidx = clkspec->args[1]; in cpg_mssr_clk_src_twocell_get()
280 struct device *dev = priv->dev; in cpg_mssr_clk_src_twocell_get()
286 switch (clkspec->args[0]) { in cpg_mssr_clk_src_twocell_get()
289 if (clkidx > priv->last_dt_core_clk) { in cpg_mssr_clk_src_twocell_get()
292 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
294 clk = priv->clks[clkidx]; in cpg_mssr_clk_src_twocell_get()
299 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
301 range_check = 7 - (clkidx % 10); in cpg_mssr_clk_src_twocell_get()
304 range_check = 31 - (clkidx % 100); in cpg_mssr_clk_src_twocell_get()
306 if (range_check < 0 || idx >= priv->num_mod_clks) { in cpg_mssr_clk_src_twocell_get()
309 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
311 clk = priv->clks[priv->num_core_clks + idx]; in cpg_mssr_clk_src_twocell_get()
315 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); in cpg_mssr_clk_src_twocell_get()
316 return ERR_PTR(-EINVAL); in cpg_mssr_clk_src_twocell_get()
324 clkspec->args[0], clkspec->args[1], clk, in cpg_mssr_clk_src_twocell_get()
333 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; in cpg_mssr_register_core_clk()
334 struct device *dev = priv->dev; in cpg_mssr_register_core_clk()
335 unsigned int id = core->id, div = core->div; in cpg_mssr_register_core_clk()
338 WARN_DEBUG(id >= priv->num_core_clks); in cpg_mssr_register_core_clk()
339 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_core_clk()
341 switch (core->type) { in cpg_mssr_register_core_clk()
343 clk = of_clk_get_by_name(priv->np, core->name); in cpg_mssr_register_core_clk()
349 WARN_DEBUG(core->parent >= priv->num_core_clks); in cpg_mssr_register_core_clk()
350 parent = priv->clks[core->parent]; in cpg_mssr_register_core_clk()
358 if (core->type == CLK_TYPE_DIV6_RO) in cpg_mssr_register_core_clk()
360 div *= (readl(priv->base + core->offset) & 0x3f) + 1; in cpg_mssr_register_core_clk()
362 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()
363 clk = cpg_div6_register(core->name, 1, &parent_name, in cpg_mssr_register_core_clk()
364 priv->base + core->offset, in cpg_mssr_register_core_clk()
365 &priv->notifiers); in cpg_mssr_register_core_clk()
367 clk = clk_register_fixed_factor(NULL, core->name, in cpg_mssr_register_core_clk()
369 core->mult, div); in cpg_mssr_register_core_clk()
374 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, in cpg_mssr_register_core_clk()
375 core->mult); in cpg_mssr_register_core_clk()
379 if (info->cpg_clk_register) in cpg_mssr_register_core_clk()
380 clk = info->cpg_clk_register(dev, core, info, in cpg_mssr_register_core_clk()
381 priv->clks, priv->base, in cpg_mssr_register_core_clk()
382 &priv->notifiers); in cpg_mssr_register_core_clk()
385 core->name, core->type); in cpg_mssr_register_core_clk()
393 priv->clks[id] = clk; in cpg_mssr_register_core_clk()
398 core->name, PTR_ERR(clk)); in cpg_mssr_register_core_clk()
406 struct device *dev = priv->dev; in cpg_mssr_register_mod_clk()
407 unsigned int id = mod->id; in cpg_mssr_register_mod_clk()
413 WARN_DEBUG(id < priv->num_core_clks); in cpg_mssr_register_mod_clk()
414 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
415 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); in cpg_mssr_register_mod_clk()
416 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); in cpg_mssr_register_mod_clk()
418 if (!mod->name) { in cpg_mssr_register_mod_clk()
423 parent = priv->clks[mod->parent]; in cpg_mssr_register_mod_clk()
431 clk = ERR_PTR(-ENOMEM); in cpg_mssr_register_mod_clk()
435 init.name = mod->name; in cpg_mssr_register_mod_clk()
442 clock->index = id - priv->num_core_clks; in cpg_mssr_register_mod_clk()
443 clock->priv = priv; in cpg_mssr_register_mod_clk()
444 clock->hw.init = &init; in cpg_mssr_register_mod_clk()
446 for (i = 0; i < info->num_crit_mod_clks; i++) in cpg_mssr_register_mod_clk()
447 if (id == info->crit_mod_clks[i] && in cpg_mssr_register_mod_clk()
448 cpg_mstp_clock_is_enabled(&clock->hw)) { in cpg_mssr_register_mod_clk()
449 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", in cpg_mssr_register_mod_clk()
450 mod->name); in cpg_mssr_register_mod_clk()
460 for (i = 0; i < priv->num_reserved_ids; i++) { in cpg_mssr_register_mod_clk()
461 if (id == priv->reserved_ids[i]) { in cpg_mssr_register_mod_clk()
462 dev_info(dev, "Ignore Linux non-assigned mod (%s)\n", mod->name); in cpg_mssr_register_mod_clk()
468 clk = clk_register(NULL, &clock->hw); in cpg_mssr_register_mod_clk()
473 priv->clks[id] = clk; in cpg_mssr_register_mod_clk()
474 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); in cpg_mssr_register_mod_clk()
479 mod->name, PTR_ERR(clk)); in cpg_mssr_register_mod_clk()
496 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) in cpg_mssr_is_pm_clk()
499 switch (clkspec->args[0]) { in cpg_mssr_is_pm_clk()
501 for (i = 0; i < pd->num_core_pm_clks; i++) in cpg_mssr_is_pm_clk()
502 if (clkspec->args[1] == pd->core_pm_clks[i]) in cpg_mssr_is_pm_clk()
517 struct device_node *np = dev->of_node; in cpg_mssr_attach_dev()
524 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); in cpg_mssr_attach_dev()
525 return -EPROBE_DEFER; in cpg_mssr_attach_dev()
528 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, in cpg_mssr_attach_dev()
578 struct device_node *np = dev->of_node; in cpg_mssr_add_clk_domain()
586 return -ENOMEM; in cpg_mssr_add_clk_domain()
588 pd->num_core_pm_clks = num_core_pm_clks; in cpg_mssr_add_clk_domain()
589 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); in cpg_mssr_add_clk_domain()
591 genpd = &pd->genpd; in cpg_mssr_add_clk_domain()
592 genpd->name = np->name; in cpg_mssr_add_clk_domain()
593 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | in cpg_mssr_add_clk_domain()
595 genpd->attach_dev = cpg_mssr_attach_dev; in cpg_mssr_add_clk_domain()
596 genpd->detach_dev = cpg_mssr_detach_dev; in cpg_mssr_add_clk_domain()
622 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); in cpg_mssr_reset()
625 writel(bitmask, priv->base + priv->reset_regs[reg]); in cpg_mssr_reset()
631 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); in cpg_mssr_reset()
643 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); in cpg_mssr_assert()
645 writel(bitmask, priv->base + priv->reset_regs[reg]); in cpg_mssr_assert()
657 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); in cpg_mssr_deassert()
659 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); in cpg_mssr_deassert()
671 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); in cpg_mssr_status()
685 unsigned int unpacked = reset_spec->args[0]; in cpg_mssr_reset_xlate()
688 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { in cpg_mssr_reset_xlate()
689 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); in cpg_mssr_reset_xlate()
690 return -EINVAL; in cpg_mssr_reset_xlate()
698 priv->rcdev.ops = &cpg_mssr_reset_ops; in cpg_mssr_reset_controller_register()
699 priv->rcdev.of_node = priv->dev->of_node; in cpg_mssr_reset_controller_register()
700 priv->rcdev.of_reset_n_cells = 1; in cpg_mssr_reset_controller_register()
701 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; in cpg_mssr_reset_controller_register()
702 priv->rcdev.nr_resets = priv->num_mod_clks; in cpg_mssr_reset_controller_register()
703 return devm_reset_controller_register(priv->dev, &priv->rcdev); in cpg_mssr_reset_controller_register()
716 .compatible = "renesas,r7s9210-cpg-mssr",
722 .compatible = "renesas,r8a7742-cpg-mssr",
728 .compatible = "renesas,r8a7743-cpg-mssr",
731 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
733 .compatible = "renesas,r8a7744-cpg-mssr",
739 .compatible = "renesas,r8a7745-cpg-mssr",
745 .compatible = "renesas,r8a77470-cpg-mssr",
751 .compatible = "renesas,r8a774a1-cpg-mssr",
757 .compatible = "renesas,r8a774b1-cpg-mssr",
763 .compatible = "renesas,r8a774c0-cpg-mssr",
769 .compatible = "renesas,r8a774e1-cpg-mssr",
775 .compatible = "renesas,r8a7790-cpg-mssr",
781 .compatible = "renesas,r8a7791-cpg-mssr",
784 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
786 .compatible = "renesas,r8a7793-cpg-mssr",
792 .compatible = "renesas,r8a7792-cpg-mssr",
798 .compatible = "renesas,r8a7794-cpg-mssr",
804 .compatible = "renesas,r8a7795-cpg-mssr",
810 .compatible = "renesas,r8a7796-cpg-mssr",
816 .compatible = "renesas,r8a77961-cpg-mssr",
822 .compatible = "renesas,r8a77965-cpg-mssr",
828 .compatible = "renesas,r8a77970-cpg-mssr",
834 .compatible = "renesas,r8a77980-cpg-mssr",
840 .compatible = "renesas,r8a77990-cpg-mssr",
846 .compatible = "renesas,r8a77995-cpg-mssr",
852 .compatible = "renesas,r8a779a0-cpg-mssr",
858 .compatible = "renesas,r8a779f0-cpg-mssr",
864 .compatible = "renesas,r8a779g0-cpg-mssr",
870 .compatible = "renesas,r8a779h0-cpg-mssr",
893 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_suspend_noirq()
894 if (priv->smstpcr_saved[reg].mask) in cpg_mssr_suspend_noirq()
895 priv->smstpcr_saved[reg].val = in cpg_mssr_suspend_noirq()
896 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
897 readb(priv->base + priv->control_regs[reg]) : in cpg_mssr_suspend_noirq()
898 readl(priv->base + priv->control_regs[reg]); in cpg_mssr_suspend_noirq()
901 /* Save core clocks */ in cpg_mssr_suspend_noirq()
902 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); in cpg_mssr_suspend_noirq()
918 /* Restore core clocks */ in cpg_mssr_resume_noirq()
919 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); in cpg_mssr_resume_noirq()
921 /* Restore module clocks */ in cpg_mssr_resume_noirq()
922 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { in cpg_mssr_resume_noirq()
923 mask = priv->smstpcr_saved[reg].mask; in cpg_mssr_resume_noirq()
927 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
928 oldval = readb(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
930 oldval = readl(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
932 newval |= priv->smstpcr_saved[reg].val & mask; in cpg_mssr_resume_noirq()
936 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
937 writeb(newval, priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
939 readb(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
940 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
943 writel(newval, priv->base + priv->control_regs[reg]); in cpg_mssr_resume_noirq()
945 /* Wait until enabled clocks are really enabled */ in cpg_mssr_resume_noirq()
946 mask &= ~priv->smstpcr_saved[reg].val; in cpg_mssr_resume_noirq()
950 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], in cpg_mssr_resume_noirq()
971 kfree(priv->reserved_ids); in cpg_mssr_reserved_exit()
984 * Because clk_disable_unused() will disable all unused clocks, the device which is assigned in cpg_mssr_reserved_init()
985 * to a non-Linux system will be disabled when Linux is booted. in cpg_mssr_reserved_init()
987 * To avoid such situation, renesas-cpg-mssr assumes the device which has in cpg_mssr_reserved_init()
988 * status = "reserved" is assigned to a non-Linux system, and adds CLK_IGNORE_UNUSED flag in cpg_mssr_reserved_init()
989 * to its CPG_MOD clocks. in cpg_mssr_reserved_init()
995 * => clocks = <&cpg CPG_MOD 202>, in cpg_mssr_reserved_init()
996 * <&cpg CPG_CORE R8A7795_CLK_S3D1>, in cpg_mssr_reserved_init()
1006 of_for_each_phandle(&it, rc, node, "clocks", "#clock-cells", -1) { in cpg_mssr_reserved_init()
1009 if (it.node != priv->np) in cpg_mssr_reserved_init()
1021 return -ENOMEM; in cpg_mssr_reserved_init()
1024 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init()
1029 ids[num] = info->num_total_core_clks + idx; in cpg_mssr_reserved_init()
1035 priv->num_reserved_ids = num; in cpg_mssr_reserved_init()
1036 priv->reserved_ids = ids; in cpg_mssr_reserved_init()
1049 if (info->init) { in cpg_mssr_common_init()
1050 error = info->init(dev); in cpg_mssr_common_init()
1055 nclks = info->num_total_core_clks + info->num_hw_mod_clks; in cpg_mssr_common_init()
1058 return -ENOMEM; in cpg_mssr_common_init()
1060 priv->np = np; in cpg_mssr_common_init()
1061 priv->dev = dev; in cpg_mssr_common_init()
1062 spin_lock_init(&priv->rmw_lock); in cpg_mssr_common_init()
1064 priv->base = of_iomap(np, 0); in cpg_mssr_common_init()
1065 if (!priv->base) { in cpg_mssr_common_init()
1066 error = -ENOMEM; in cpg_mssr_common_init()
1070 priv->num_core_clks = info->num_total_core_clks; in cpg_mssr_common_init()
1071 priv->num_mod_clks = info->num_hw_mod_clks; in cpg_mssr_common_init()
1072 priv->last_dt_core_clk = info->last_dt_core_clk; in cpg_mssr_common_init()
1073 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); in cpg_mssr_common_init()
1074 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
1075 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { in cpg_mssr_common_init()
1076 priv->status_regs = mstpsr; in cpg_mssr_common_init()
1077 priv->control_regs = smstpcr; in cpg_mssr_common_init()
1078 priv->reset_regs = srcr; in cpg_mssr_common_init()
1079 priv->reset_clear_regs = srstclr; in cpg_mssr_common_init()
1080 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_common_init()
1081 priv->control_regs = stbcr; in cpg_mssr_common_init()
1082 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { in cpg_mssr_common_init()
1083 priv->status_regs = mstpsr_for_gen4; in cpg_mssr_common_init()
1084 priv->control_regs = mstpcr_for_gen4; in cpg_mssr_common_init()
1085 priv->reset_regs = srcr_for_gen4; in cpg_mssr_common_init()
1086 priv->reset_clear_regs = srstclr_for_gen4; in cpg_mssr_common_init()
1088 error = -EINVAL; in cpg_mssr_common_init()
1093 priv->clks[i] = ERR_PTR(-ENOENT); in cpg_mssr_common_init()
1110 if (priv->base) in cpg_mssr_common_init()
1111 iounmap(priv->base); in cpg_mssr_common_init()
1127 for (i = 0; i < info->num_early_core_clks; i++) in cpg_mssr_early_init()
1128 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, in cpg_mssr_early_init()
1131 for (i = 0; i < info->num_early_mod_clks; i++) in cpg_mssr_early_init()
1132 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, in cpg_mssr_early_init()
1139 struct device *dev = &pdev->dev; in cpg_mssr_probe()
1140 struct device_node *np = dev->of_node; in cpg_mssr_probe()
1149 error = cpg_mssr_common_init(dev, dev->of_node, info); in cpg_mssr_probe()
1155 priv->dev = dev; in cpg_mssr_probe()
1158 for (i = 0; i < info->num_core_clks; i++) in cpg_mssr_probe()
1159 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); in cpg_mssr_probe()
1161 for (i = 0; i < info->num_mod_clks; i++) in cpg_mssr_probe()
1162 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); in cpg_mssr_probe()
1170 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, in cpg_mssr_probe()
1171 info->num_core_pm_clks); in cpg_mssr_probe()
1176 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_probe()
1189 .name = "renesas-cpg-mssr",
1215 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");