Lines Matching +full:0 +full:x1740
35 .l_reg = 0x0004,
36 .m_reg = 0x0008,
37 .n_reg = 0x000c,
38 .config_reg = 0x0014,
39 .mode_reg = 0x0000,
40 .status_reg = 0x001c,
53 .enable_reg = 0x1480,
54 .enable_mask = BIT(0),
66 .l_reg = 0x1dc4,
67 .m_reg = 0x1dc8,
68 .n_reg = 0x1dcc,
69 .config_reg = 0x1dd4,
70 .mode_reg = 0x1dc0,
71 .status_reg = 0x1ddc,
84 .enable_reg = 0x1480,
97 { P_XO, 0 },
107 { P_XO, 0 },
119 .cmd_rcgr = 0x0150,
131 .cmd_rcgr = 0x0190,
143 .cmd_rcgr = 0x0120,
155 .l_reg = 0x0044,
156 .m_reg = 0x0048,
157 .n_reg = 0x004c,
158 .config_reg = 0x0054,
159 .mode_reg = 0x0040,
160 .status_reg = 0x005c,
173 .enable_reg = 0x1480,
191 .cmd_rcgr = 0x03d4,
205 F(19200000, P_XO, 1, 0, 0),
206 F(37500000, P_GPLL0, 16, 0, 0),
207 F(50000000, P_GPLL0, 12, 0, 0),
212 .cmd_rcgr = 0x0660,
226 F(4800000, P_XO, 4, 0, 0),
227 F(9600000, P_XO, 2, 0, 0),
229 F(19200000, P_XO, 1, 0, 0),
231 F(50000000, P_GPLL0, 12, 0, 0),
236 .cmd_rcgr = 0x064c,
250 .cmd_rcgr = 0x06e0,
263 .cmd_rcgr = 0x06cc,
277 .cmd_rcgr = 0x0760,
290 .cmd_rcgr = 0x074c,
304 .cmd_rcgr = 0x07e0,
317 .cmd_rcgr = 0x07cc,
331 .cmd_rcgr = 0x0860,
344 .cmd_rcgr = 0x084c,
358 .cmd_rcgr = 0x08e0,
371 .cmd_rcgr = 0x08cc,
389 F(19200000, P_XO, 1, 0, 0),
392 F(40000000, P_GPLL0, 15, 0, 0),
394 F(48000000, P_GPLL0, 12.5, 0, 0),
398 F(60000000, P_GPLL0, 10, 0, 0),
399 F(63160000, P_GPLL0, 9.5, 0, 0),
404 .cmd_rcgr = 0x068c,
418 .cmd_rcgr = 0x070c,
432 .cmd_rcgr = 0x078c,
446 .cmd_rcgr = 0x080c,
460 .cmd_rcgr = 0x088c,
474 .cmd_rcgr = 0x090c,
488 .cmd_rcgr = 0x09a0,
501 .cmd_rcgr = 0x098c,
515 .cmd_rcgr = 0x0a20,
528 .cmd_rcgr = 0x0a0c,
542 .cmd_rcgr = 0x0aa0,
555 .cmd_rcgr = 0x0a8c,
569 .cmd_rcgr = 0x0b20,
582 .cmd_rcgr = 0x0b0c,
596 .cmd_rcgr = 0x0ba0,
609 .cmd_rcgr = 0x0b8c,
623 .cmd_rcgr = 0x0c20,
636 .cmd_rcgr = 0x0c0c,
650 .cmd_rcgr = 0x09cc,
664 .cmd_rcgr = 0x0a4c,
678 .cmd_rcgr = 0x0acc,
692 .cmd_rcgr = 0x0b4c,
706 .cmd_rcgr = 0x0bcc,
720 .cmd_rcgr = 0x0c4c,
734 F(50000000, P_GPLL0, 12, 0, 0),
735 F(100000000, P_GPLL0, 6, 0, 0),
740 F(50000000, P_GPLL0, 12, 0, 0),
741 F(75000000, P_GPLL0, 8, 0, 0),
742 F(100000000, P_GPLL0, 6, 0, 0),
743 F(150000000, P_GPLL0, 4, 0, 0),
748 .cmd_rcgr = 0x1050,
761 F(50000000, P_GPLL0, 12, 0, 0),
762 F(75000000, P_GPLL0, 8, 0, 0),
763 F(100000000, P_GPLL0, 6, 0, 0),
764 F(150000000, P_GPLL0, 4, 0, 0),
769 .cmd_rcgr = 0x1090,
782 F(19200000, P_XO, 1, 0, 0),
787 F(4800000, P_XO, 4, 0, 0),
791 F(9600000, P_XO, 2, 0, 0),
793 F(19200000, P_XO, 1, 0, 0),
800 .cmd_rcgr = 0x1904,
814 .cmd_rcgr = 0x1944,
828 .cmd_rcgr = 0x1984,
842 F(60000000, P_GPLL0, 10, 0, 0),
847 .cmd_rcgr = 0x0cd0,
864 F(50000000, P_GPLL0, 12, 0, 0),
865 F(100000000, P_GPLL0, 6, 0, 0),
866 F(200000000, P_GPLL0, 3, 0, 0),
875 F(50000000, P_GPLL0, 12, 0, 0),
876 F(100000000, P_GPLL0, 6, 0, 0),
877 F(192000000, P_GPLL4, 4, 0, 0),
878 F(200000000, P_GPLL0, 3, 0, 0),
879 F(384000000, P_GPLL4, 2, 0, 0),
891 .cmd_rcgr = 0x04d0,
900 .cmd_rcgr = 0x0510,
914 .cmd_rcgr = 0x0550,
928 .cmd_rcgr = 0x0590,
947 .cmd_rcgr = 0x0d90,
961 F(60000000, P_GPLL0, 10, 0, 0),
966 .cmd_rcgr = 0x03e8,
979 F(60000000, P_GPLL0, 10, 0, 0),
980 F(75000000, P_GPLL0, 8, 0, 0),
985 .cmd_rcgr = 0x0490,
998 F(480000000, P_GPLL1, 1, 0, 0),
1003 { P_XO, 0 },
1008 .cmd_rcgr = 0x0440,
1024 F(9600000, P_XO, 2, 0, 0),
1029 .cmd_rcgr = 0x0458,
1042 F(60000000, P_GPLL0, 10, 0, 0),
1043 F(75000000, P_GPLL0, 8, 0, 0),
1048 .cmd_rcgr = 0x041c,
1061 .enable_reg = 0x1484,
1074 .halt_reg = 0x0d44,
1077 .enable_reg = 0x1484,
1091 .halt_reg = 0x05c4,
1094 .enable_reg = 0x1484,
1108 .halt_reg = 0x0648,
1110 .enable_reg = 0x0648,
1111 .enable_mask = BIT(0),
1125 .halt_reg = 0x0644,
1127 .enable_reg = 0x0644,
1128 .enable_mask = BIT(0),
1142 .halt_reg = 0x06c8,
1144 .enable_reg = 0x06c8,
1145 .enable_mask = BIT(0),
1159 .halt_reg = 0x06c4,
1161 .enable_reg = 0x06c4,
1162 .enable_mask = BIT(0),
1176 .halt_reg = 0x0748,
1178 .enable_reg = 0x0748,
1179 .enable_mask = BIT(0),
1193 .halt_reg = 0x0744,
1195 .enable_reg = 0x0744,
1196 .enable_mask = BIT(0),
1210 .halt_reg = 0x07c8,
1212 .enable_reg = 0x07c8,
1213 .enable_mask = BIT(0),
1227 .halt_reg = 0x07c4,
1229 .enable_reg = 0x07c4,
1230 .enable_mask = BIT(0),
1244 .halt_reg = 0x0848,
1246 .enable_reg = 0x0848,
1247 .enable_mask = BIT(0),
1261 .halt_reg = 0x0844,
1263 .enable_reg = 0x0844,
1264 .enable_mask = BIT(0),
1278 .halt_reg = 0x08c8,
1280 .enable_reg = 0x08c8,
1281 .enable_mask = BIT(0),
1295 .halt_reg = 0x08c4,
1297 .enable_reg = 0x08c4,
1298 .enable_mask = BIT(0),
1312 .halt_reg = 0x0684,
1314 .enable_reg = 0x0684,
1315 .enable_mask = BIT(0),
1329 .halt_reg = 0x0704,
1331 .enable_reg = 0x0704,
1332 .enable_mask = BIT(0),
1346 .halt_reg = 0x0784,
1348 .enable_reg = 0x0784,
1349 .enable_mask = BIT(0),
1363 .halt_reg = 0x0804,
1365 .enable_reg = 0x0804,
1366 .enable_mask = BIT(0),
1380 .halt_reg = 0x0884,
1382 .enable_reg = 0x0884,
1383 .enable_mask = BIT(0),
1397 .halt_reg = 0x0904,
1399 .enable_reg = 0x0904,
1400 .enable_mask = BIT(0),
1414 .halt_reg = 0x0944,
1417 .enable_reg = 0x1484,
1431 .halt_reg = 0x0988,
1433 .enable_reg = 0x0988,
1434 .enable_mask = BIT(0),
1448 .halt_reg = 0x0984,
1450 .enable_reg = 0x0984,
1451 .enable_mask = BIT(0),
1465 .halt_reg = 0x0a08,
1467 .enable_reg = 0x0a08,
1468 .enable_mask = BIT(0),
1482 .halt_reg = 0x0a04,
1484 .enable_reg = 0x0a04,
1485 .enable_mask = BIT(0),
1499 .halt_reg = 0x0a88,
1501 .enable_reg = 0x0a88,
1502 .enable_mask = BIT(0),
1516 .halt_reg = 0x0a84,
1518 .enable_reg = 0x0a84,
1519 .enable_mask = BIT(0),
1533 .halt_reg = 0x0b08,
1535 .enable_reg = 0x0b08,
1536 .enable_mask = BIT(0),
1550 .halt_reg = 0x0b04,
1552 .enable_reg = 0x0b04,
1553 .enable_mask = BIT(0),
1567 .halt_reg = 0x0b88,
1569 .enable_reg = 0x0b88,
1570 .enable_mask = BIT(0),
1584 .halt_reg = 0x0b84,
1586 .enable_reg = 0x0b84,
1587 .enable_mask = BIT(0),
1601 .halt_reg = 0x0c08,
1603 .enable_reg = 0x0c08,
1604 .enable_mask = BIT(0),
1618 .halt_reg = 0x0c04,
1620 .enable_reg = 0x0c04,
1621 .enable_mask = BIT(0),
1635 .halt_reg = 0x09c4,
1637 .enable_reg = 0x09c4,
1638 .enable_mask = BIT(0),
1652 .halt_reg = 0x0a44,
1654 .enable_reg = 0x0a44,
1655 .enable_mask = BIT(0),
1669 .halt_reg = 0x0ac4,
1671 .enable_reg = 0x0ac4,
1672 .enable_mask = BIT(0),
1686 .halt_reg = 0x0b44,
1688 .enable_reg = 0x0b44,
1689 .enable_mask = BIT(0),
1703 .halt_reg = 0x0bc4,
1705 .enable_reg = 0x0bc4,
1706 .enable_mask = BIT(0),
1720 .halt_reg = 0x0c44,
1722 .enable_reg = 0x0c44,
1723 .enable_mask = BIT(0),
1737 .halt_reg = 0x0e04,
1740 .enable_reg = 0x1484,
1754 .halt_reg = 0x104c,
1757 .enable_reg = 0x1484,
1771 .halt_reg = 0x1048,
1774 .enable_reg = 0x1484,
1788 .halt_reg = 0x1050,
1791 .enable_reg = 0x1484,
1806 .halt_reg = 0x108c,
1809 .enable_reg = 0x1484,
1810 .enable_mask = BIT(0),
1823 .halt_reg = 0x1088,
1826 .enable_reg = 0x1484,
1840 .halt_reg = 0x1090,
1843 .enable_reg = 0x1484,
1858 .halt_reg = 0x1900,
1860 .enable_reg = 0x1900,
1861 .enable_mask = BIT(0),
1875 .halt_reg = 0x1940,
1877 .enable_reg = 0x1940,
1878 .enable_mask = BIT(0),
1892 .halt_reg = 0x1980,
1894 .enable_reg = 0x1980,
1895 .enable_mask = BIT(0),
1909 .halt_reg = 0x11c0,
1911 .enable_reg = 0x11c0,
1912 .enable_mask = BIT(0),
1925 .halt_reg = 0x024c,
1927 .enable_reg = 0x024c,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x0248,
1944 .enable_reg = 0x0248,
1945 .enable_mask = BIT(0),
1958 .halt_reg = 0x0280,
1960 .enable_reg = 0x0280,
1961 .enable_mask = BIT(0),
1974 .halt_reg = 0x0284,
1976 .enable_reg = 0x0284,
1977 .enable_mask = BIT(0),
1990 .halt_reg = 0x0ccc,
1992 .enable_reg = 0x0ccc,
1993 .enable_mask = BIT(0),
2007 .halt_reg = 0x0cc4,
2009 .enable_reg = 0x0cc4,
2010 .enable_mask = BIT(0),
2023 .halt_reg = 0x0cc8,
2025 .enable_reg = 0x0cc8,
2026 .enable_mask = BIT(0),
2039 .halt_reg = 0x0d04,
2042 .enable_reg = 0x1484,
2056 .halt_reg = 0x04c8,
2058 .enable_reg = 0x04c8,
2059 .enable_mask = BIT(0),
2072 .halt_reg = 0x04c4,
2074 .enable_reg = 0x04c4,
2075 .enable_mask = BIT(0),
2089 .halt_reg = 0x04e8,
2091 .enable_reg = 0x04e8,
2092 .enable_mask = BIT(0),
2105 .halt_reg = 0x04e4,
2107 .enable_reg = 0x04e4,
2108 .enable_mask = BIT(0),
2121 .halt_reg = 0x0508,
2123 .enable_reg = 0x0508,
2124 .enable_mask = BIT(0),
2137 .halt_reg = 0x0504,
2139 .enable_reg = 0x0504,
2140 .enable_mask = BIT(0),
2154 .halt_reg = 0x0548,
2156 .enable_reg = 0x0548,
2157 .enable_mask = BIT(0),
2170 .halt_reg = 0x0544,
2172 .enable_reg = 0x0544,
2173 .enable_mask = BIT(0),
2187 .halt_reg = 0x0588,
2189 .enable_reg = 0x0588,
2190 .enable_mask = BIT(0),
2203 .halt_reg = 0x0584,
2205 .enable_reg = 0x0584,
2206 .enable_mask = BIT(0),
2220 .halt_reg = 0x0108,
2222 .enable_reg = 0x0108,
2223 .enable_mask = BIT(0),
2237 .halt_reg = 0x0d84,
2239 .enable_reg = 0x0d84,
2240 .enable_mask = BIT(0),
2253 .halt_reg = 0x0d88,
2255 .enable_reg = 0x0d88,
2256 .enable_mask = BIT(0),
2270 .halt_reg = 0x04ac,
2272 .enable_reg = 0x04ac,
2273 .enable_mask = BIT(0),
2286 .halt_reg = 0x04b4,
2288 .enable_reg = 0x04b4,
2289 .enable_mask = BIT(0),
2302 .halt_reg = 0x03c8,
2304 .enable_reg = 0x03c8,
2305 .enable_mask = BIT(0),
2319 .halt_reg = 0x03d0,
2321 .enable_reg = 0x03d0,
2322 .enable_mask = BIT(0),
2336 .halt_reg = 0x03cc,
2338 .enable_reg = 0x03cc,
2339 .enable_mask = BIT(0),
2352 .halt_reg = 0x0488,
2354 .enable_reg = 0x0488,
2355 .enable_mask = BIT(0),
2368 .halt_reg = 0x0484,
2370 .enable_reg = 0x0484,
2371 .enable_mask = BIT(0),
2385 .halt_reg = 0x0408,
2387 .enable_reg = 0x0408,
2388 .enable_mask = BIT(0),
2401 .halt_reg = 0x0410,
2403 .enable_reg = 0x0410,
2404 .enable_mask = BIT(0),
2418 .halt_reg = 0x0414,
2420 .enable_reg = 0x0414,
2421 .enable_mask = BIT(0),
2435 .halt_reg = 0x0418,
2437 .enable_reg = 0x0418,
2438 .enable_mask = BIT(0),
2451 .halt_reg = 0x040c,
2453 .enable_reg = 0x040c,
2454 .enable_mask = BIT(0),
2468 .gdscr = 0x404,
2563 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2564 [GCC_USB_HS_BCR] = { 0x0480 },
2565 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2576 .max_register = 0x1a80,
2739 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2740 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2741 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2742 [GCC_IMEM_BCR] = { 0x0200 },
2743 [GCC_MMSS_BCR] = { 0x0240 },
2744 [GCC_QDSS_BCR] = { 0x0300 },
2745 [GCC_USB_30_BCR] = { 0x03c0 },
2746 [GCC_USB3_PHY_BCR] = { 0x03fc },
2747 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2748 [GCC_USB_HS_BCR] = { 0x0480 },
2749 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2750 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2751 [GCC_SDCC1_BCR] = { 0x04c0 },
2752 [GCC_SDCC2_BCR] = { 0x0500 },
2753 [GCC_SDCC3_BCR] = { 0x0540 },
2754 [GCC_SDCC4_BCR] = { 0x0580 },
2755 [GCC_BLSP1_BCR] = { 0x05c0 },
2756 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2757 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2758 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2759 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2760 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2761 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2762 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2763 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2764 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2765 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2766 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2767 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2768 [GCC_BLSP2_BCR] = { 0x0940 },
2769 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2770 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2771 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2772 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2773 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2774 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2775 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2776 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2777 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2778 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2779 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2780 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2781 [GCC_PDM_BCR] = { 0x0cc0 },
2782 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2783 [GCC_TSIF_BCR] = { 0x0d80 },
2784 [GCC_TCSR_BCR] = { 0x0dc0 },
2785 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2786 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2787 [GCC_TLMM_BCR] = { 0x0e80 },
2788 [GCC_MPM_BCR] = { 0x0ec0 },
2789 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2790 [GCC_SPMI_BCR] = { 0x0fc0 },
2791 [GCC_SPDM_BCR] = { 0x1000 },
2792 [GCC_CE1_BCR] = { 0x1040 },
2793 [GCC_CE2_BCR] = { 0x1080 },
2794 [GCC_BIMC_BCR] = { 0x1100 },
2795 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2796 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2797 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2798 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2799 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2800 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2801 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2802 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2803 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2804 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2805 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2806 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2807 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2808 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2809 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2810 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2811 [GCC_DEHR_BCR] = { 0x1300 },
2812 [GCC_RBCPR_BCR] = { 0x1380 },
2813 [GCC_MSS_RESTART] = { 0x1680 },
2814 [GCC_LPASS_RESTART] = { 0x16c0 },
2815 [GCC_WCSS_RESTART] = { 0x1700 },
2816 [GCC_VENUS_RESTART] = { 0x1740 },
2827 .max_register = 0x1fc0,