Lines Matching +full:sm8750 +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
1060 	tristate "SM8750 Display Clock Controller"
1066 	  SM8750 devices.
1180 	tristate "SM8750 Global Clock Controller"
1184 	  Support for the global clock controller on SM8750 devices.
1294 	  Say Y if you want to toggle LPASS-adjacent resets within
1314 	tristate "SM8750 TCSR Clock Controller"
1318 	  Support for the TCSR clock controller on SM8750 devices.
1393 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1395 	  Support for the high-frequency PLLs present on Qualcomm devices.
1402 	  Support for the Krait ACC and GCC clock controllers. Say Y