Lines Matching +full:sm8550 +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
954 	tristate "SM8550 Camera Clock Controller"
958 	  Support for the camera clock controller on SM8550 devices.
1050 	tristate "SM8550 Display Clock Controller"
1055 	  SAR2130P, SM8550 or SM8650 devices.
1162 	tristate "SM8550 Global Clock Controller"
1166 	  Support for the global clock controller on SM8550 devices.
1271 	tristate "SM8550 Graphics Clock Controller"
1275 	  Support for the graphics clock controller on SM8550 devices.
1294 	  Say Y if you want to toggle LPASS-adjacent resets within
1298 	tristate "SM8550 TCSR Clock Controller"
1302 	  Support for the TCSR clock controller on SM8550 devices.
1373 	tristate "SM8550 Video Clock Controller"
1379 	  SM8550 or SM8650 devices.
1393 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1395 	  Support for the high-frequency PLLs present on Qualcomm devices.
1402 	  Support for the Krait ACC and GCC clock controllers. Say Y