Lines Matching +full:sar2130p +full:- +full:gcc

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
621 	tristate "SAR2130P Global Clock Controller"
625 	  Support for the global clock controller on SAR2130P devices.
630 	tristate "SAR2130P Graphics clock controller"
634 	  Support for the graphics clock controller on SAR2130P devices.
1055 	  SAR2130P, SM8550 or SM8650 devices.
1294 	  Say Y if you want to toggle LPASS-adjacent resets within
1393 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1395 	  Support for the high-frequency PLLs present on Qualcomm devices.
1402 	  Support for the Krait ACC and GCC clock controllers. Say Y