Lines Matching +full:gcc +full:- +full:sm6115

1 # SPDX-License-Identifier: GPL-2.0-only
206 	  CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 	  the output clocks to the networking hardware and GCC blocks.
980 	tristate "SM6115 Display Clock Controller"
985 	  SM6115/SM4250 devices.
1080 	tristate "SM6115 and SM4250 Global Clock Controller"
1084 	  Support for the global clock controller on SM6115 and SM4250 devices.
1198 	tristate "SM6115 Graphics Clock Controller"
1202 	  Support for the graphics clock controller on SM6115 devices.
1289 	tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller"
1293 	  Support for the LPASS clock controller on SM6115 devices.
1294 	  Say Y if you want to toggle LPASS-adjacent resets within
1393 	tristate "High-Frequency PLL (HFPLL) Clock Controller"
1395 	  Support for the high-frequency PLLs present on Qualcomm devices.
1402 	  Support for the Krait ACC and GCC clock controllers. Say Y