Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
22 * 16-bit register address: the lower 8 bits of the register address come
55 #define VC7_IOD_MAX_DIVISOR 0x1ffffff /* 25-bit */
63 #define VC7_FOD_2ND_INT_MAX 0x1ffff /* 17-bit */
181 unsigned int idx = clkspec->args[0]; in vc7_of_clk_get()
183 if (idx >= vc7->chip_info->num_outputs) in vc7_of_clk_get()
184 return ERR_PTR(-EINVAL); in vc7_of_clk_get()
186 return &vc7->clk_out[idx].hw; in vc7_of_clk_get()
220 * vc7_64_mul_64_to_128() - Multiply two u64 and return an unsigned 128-bit integer
225 * @hi: The upper 64-bits of the 128-bit product.
226 * @lo: The lower 64-bits of the 128-bit product.
253 * vc7_128_div_64_to_64() - Divides a 128-bit uint by a 64-bit divisor, return a 64-bit quotient.
255 * @numhi: The uppper 64-bits of the dividend.
256 * @numlo: The lower 64-bits of the dividend.
264 * Return: The 64-bit quotient of the division.
316 * numhi < den. The expression (-shift & 63) is the same as (64 - in vc7_128_div_64_to_64()
325 numhi |= (numlo >> (-shift & 63)) & (-(s64)shift >> 63); in vc7_128_div_64_to_64()
346 qhat -= (c1 - c2 > den) ? 2 : 1; in vc7_128_div_64_to_64()
350 rem = numhi * b + num1 - q1 * den; in vc7_128_div_64_to_64()
360 qhat -= (c1 - c2 > den) ? 2 : 1; in vc7_128_div_64_to_64()
365 *r = (rem * b + num0 - q0 * den) >> shift; in vc7_128_div_64_to_64()
378 map->type = VC7_IOD, in vc7_get_bank_clk()
379 map->src.iod = &vc7->clk_iod[0]; in vc7_get_bank_clk()
382 map->type = VC7_IOD, in vc7_get_bank_clk()
383 map->src.iod = &vc7->clk_iod[1]; in vc7_get_bank_clk()
386 map->type = VC7_FOD, in vc7_get_bank_clk()
387 map->src.fod = &vc7->clk_fod[0]; in vc7_get_bank_clk()
390 map->type = VC7_FOD, in vc7_get_bank_clk()
391 map->src.fod = &vc7->clk_fod[1]; in vc7_get_bank_clk()
399 map->type = VC7_IOD, in vc7_get_bank_clk()
400 map->src.iod = &vc7->clk_iod[1]; in vc7_get_bank_clk()
403 map->type = VC7_FOD, in vc7_get_bank_clk()
404 map->src.fod = &vc7->clk_fod[0]; in vc7_get_bank_clk()
407 map->type = VC7_FOD, in vc7_get_bank_clk()
408 map->src.fod = &vc7->clk_fod[1]; in vc7_get_bank_clk()
416 map->type = VC7_FOD, in vc7_get_bank_clk()
417 map->src.fod = &vc7->clk_fod[0]; in vc7_get_bank_clk()
420 map->type = VC7_FOD, in vc7_get_bank_clk()
421 map->src.fod = &vc7->clk_fod[1]; in vc7_get_bank_clk()
424 map->type = VC7_FOD, in vc7_get_bank_clk()
425 map->src.fod = &vc7->clk_fod[2]; in vc7_get_bank_clk()
436 map->type = VC7_IOD, in vc7_get_bank_clk()
437 map->src.iod = &vc7->clk_iod[2]; in vc7_get_bank_clk()
440 map->type = VC7_FOD, in vc7_get_bank_clk()
441 map->src.fod = &vc7->clk_fod[1]; in vc7_get_bank_clk()
444 map->type = VC7_FOD, in vc7_get_bank_clk()
445 map->src.fod = &vc7->clk_fod[2]; in vc7_get_bank_clk()
462 map->type = VC7_IOD, in vc7_get_bank_clk()
463 map->src.iod = &vc7->clk_iod[2]; in vc7_get_bank_clk()
466 map->type = VC7_IOD, in vc7_get_bank_clk()
467 map->src.iod = &vc7->clk_iod[3]; in vc7_get_bank_clk()
470 map->type = VC7_FOD, in vc7_get_bank_clk()
471 map->src.fod = &vc7->clk_fod[1]; in vc7_get_bank_clk()
474 map->type = VC7_FOD, in vc7_get_bank_clk()
475 map->src.fod = &vc7->clk_fod[2]; in vc7_get_bank_clk()
489 map->type = VC7_IOD, in vc7_get_bank_clk()
490 map->src.iod = &vc7->clk_iod[2]; in vc7_get_bank_clk()
493 map->type = VC7_IOD, in vc7_get_bank_clk()
494 map->src.iod = &vc7->clk_iod[3]; in vc7_get_bank_clk()
497 map->type = VC7_FOD, in vc7_get_bank_clk()
498 map->src.fod = &vc7->clk_fod[1]; in vc7_get_bank_clk()
501 map->type = VC7_FOD, in vc7_get_bank_clk()
502 map->src.fod = &vc7->clk_fod[2]; in vc7_get_bank_clk()
513 return -1; in vc7_get_bank_clk()
522 err = regmap_bulk_read(vc7->regmap, in vc7_read_apll()
527 dev_err(&vc7->client->dev, "failed to read XO_CNFG\n"); in vc7_read_apll()
531 vc7->clk_apll.xo_ib_h_div = (val32 & VC7_REG_XO_IB_H_DIV_MASK) in vc7_read_apll()
534 err = regmap_read(vc7->regmap, in vc7_read_apll()
538 dev_err(&vc7->client->dev, "failed to read APLL_CNFG\n"); in vc7_read_apll()
542 vc7->clk_apll.en_doubler = val32 & VC7_REG_APLL_EN_DOUBLER; in vc7_read_apll()
544 err = regmap_bulk_read(vc7->regmap, in vc7_read_apll()
549 dev_err(&vc7->client->dev, "failed to read APLL_FB_DIV_FRAC\n"); in vc7_read_apll()
553 vc7->clk_apll.apll_fb_div_frac = val32 & VC7_REG_APLL_FB_DIV_FRAC_MASK; in vc7_read_apll()
555 err = regmap_bulk_read(vc7->regmap, in vc7_read_apll()
560 dev_err(&vc7->client->dev, "failed to read APLL_FB_DIV_INT\n"); in vc7_read_apll()
564 vc7->clk_apll.apll_fb_div_int = val16 & VC7_REG_APLL_FB_DIV_INT_MASK; in vc7_read_apll()
574 err = regmap_bulk_read(vc7->regmap, in vc7_read_fod()
579 dev_err(&vc7->client->dev, "failed to read FOD%d\n", idx); in vc7_read_fod()
583 vc7->clk_fod[idx].fod_1st_int = (val & VC7_REG_FOD_1ST_INT_MASK); in vc7_read_fod()
584 vc7->clk_fod[idx].fod_2nd_int = in vc7_read_fod()
586 vc7->clk_fod[idx].fod_frac = (val & VC7_REG_FOD_FRAC_MASK) in vc7_read_fod()
603 err = regmap_bulk_read(vc7->regmap, in vc7_write_fod()
608 dev_err(&vc7->client->dev, "failed to read FOD%d\n", idx); in vc7_write_fod()
613 vc7->clk_fod[idx].fod_1st_int, in vc7_write_fod()
616 vc7->clk_fod[idx].fod_2nd_int, in vc7_write_fod()
619 vc7->clk_fod[idx].fod_frac, in vc7_write_fod()
622 err = regmap_bulk_write(vc7->regmap, in vc7_write_fod()
627 dev_err(&vc7->client->dev, "failed to write FOD%d\n", idx); in vc7_write_fod()
639 err = regmap_bulk_read(vc7->regmap, in vc7_read_iod()
644 dev_err(&vc7->client->dev, "failed to read IOD%d\n", idx); in vc7_read_iod()
648 vc7->clk_iod[idx].iod_int = (val & VC7_REG_IOD_INT_MASK); in vc7_read_iod()
663 err = regmap_bulk_read(vc7->regmap, in vc7_write_iod()
668 dev_err(&vc7->client->dev, "failed to read IOD%d\n", idx); in vc7_write_iod()
673 vc7->clk_iod[idx].iod_int, in vc7_write_iod()
676 err = regmap_bulk_write(vc7->regmap, in vc7_write_iod()
681 dev_err(&vc7->client->dev, "failed to write IOD%d\n", idx); in vc7_write_iod()
693 out_num = vc7_map_index_to_output(vc7->chip_info->model, idx); in vc7_read_output()
694 err = regmap_read(vc7->regmap, in vc7_read_output()
698 dev_err(&vc7->client->dev, "failed to read ODRV_EN[%d]\n", idx); in vc7_read_output()
702 vc7->clk_out[idx].out_dis = val & VC7_REG_OUT_DIS; in vc7_read_output()
712 out_num = vc7_map_index_to_output(vc7->chip_info->model, idx); in vc7_write_output()
713 err = regmap_write_bits(vc7->regmap, in vc7_write_output()
716 vc7->clk_out[idx].out_dis); in vc7_write_output()
719 dev_err(&vc7->client->dev, "failed to write ODRV_EN[%d]\n", idx); in vc7_write_output()
732 xtal_rate = clk_get_rate(vc7->pin_xin); in vc7_get_apll_rate()
735 dev_err(&vc7->client->dev, "unable to read apll\n"); in vc7_get_apll_rate()
740 if (vc7->clk_apll.xo_ib_h_div < 2) in vc7_get_apll_rate()
743 refin_div = div64_u64(xtal_rate, vc7->clk_apll.xo_ib_h_div); in vc7_get_apll_rate()
745 if (vc7->clk_apll.en_doubler) in vc7_get_apll_rate()
749 apll_rate = (refin_div * vc7->clk_apll.apll_fb_div_int) + in vc7_get_apll_rate()
750 ((refin_div * vc7->clk_apll.apll_fb_div_frac) >> VC7_APLL_DENOMINATOR_BITS); in vc7_get_apll_rate()
752 pr_debug("%s - xo_ib_h_div: %u, apll_fb_div_int: %u, apll_fb_div_frac: %u\n", in vc7_get_apll_rate()
753 __func__, vc7->clk_apll.xo_ib_h_div, vc7->clk_apll.apll_fb_div_int, in vc7_get_apll_rate()
754 vc7->clk_apll.apll_fb_div_frac); in vc7_get_apll_rate()
755 pr_debug("%s - refin_div: %llu, apll rate: %llu\n", in vc7_get_apll_rate()
808 * There is a div-by-2 preceding the 2nd stage integer divider in vc7_calc_fod_2nd_stage_rate()
833 * 1) There is a div-by-2 preceding the 2nd stage integer divider in vc7_calc_fod_divider()
868 i--; in vc7_calc_fod_divider()
879 struct vc7_driver_data *vc7 = fod->vc7; in vc7_fod_recalc_rate()
883 err = vc7_read_fod(vc7, fod->num); in vc7_fod_recalc_rate()
885 dev_err(&vc7->client->dev, "error reading registers for %s\n", in vc7_fod_recalc_rate()
890 pr_debug("%s - %s: parent_rate: %lu\n", __func__, clk_hw_get_name(hw), parent_rate); in vc7_fod_recalc_rate()
892 fod_rate = vc7_calc_fod_2nd_stage_rate(parent_rate, fod->fod_1st_int, in vc7_fod_recalc_rate()
893 fod->fod_2nd_int, fod->fod_frac); in vc7_fod_recalc_rate()
895 pr_debug("%s - %s: fod_1st_int: %u, fod_2nd_int: %u, fod_frac: %llu\n", in vc7_fod_recalc_rate()
897 fod->fod_1st_int, fod->fod_2nd_int, fod->fod_frac); in vc7_fod_recalc_rate()
898 pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); in vc7_fod_recalc_rate()
908 pr_debug("%s - %s: requested rate: %lu, parent_rate: %lu\n", in vc7_fod_round_rate()
912 &fod->fod_1st_int, &fod->fod_2nd_int, &fod->fod_frac); in vc7_fod_round_rate()
913 fod_rate = vc7_calc_fod_2nd_stage_rate(*parent_rate, fod->fod_1st_int, in vc7_fod_round_rate()
914 fod->fod_2nd_int, fod->fod_frac); in vc7_fod_round_rate()
916 pr_debug("%s - %s: fod_1st_int: %u, fod_2nd_int: %u, fod_frac: %llu\n", in vc7_fod_round_rate()
918 fod->fod_1st_int, fod->fod_2nd_int, fod->fod_frac); in vc7_fod_round_rate()
919 pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); in vc7_fod_round_rate()
927 struct vc7_driver_data *vc7 = fod->vc7; in vc7_fod_set_rate()
930 pr_debug("%s - %s: rate: %lu, parent_rate: %lu\n", in vc7_fod_set_rate()
934 dev_err(&vc7->client->dev, in vc7_fod_set_rate()
937 return -EINVAL; in vc7_fod_set_rate()
940 vc7_write_fod(vc7, fod->num); in vc7_fod_set_rate()
942 fod_rate = vc7_calc_fod_2nd_stage_rate(parent_rate, fod->fod_1st_int, in vc7_fod_set_rate()
943 fod->fod_2nd_int, fod->fod_frac); in vc7_fod_set_rate()
945 pr_debug("%s - %s: fod_1st_int: %u, fod_2nd_int: %u, fod_frac: %llu\n", in vc7_fod_set_rate()
947 fod->fod_1st_int, fod->fod_2nd_int, fod->fod_frac); in vc7_fod_set_rate()
948 pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); in vc7_fod_set_rate()
962 struct vc7_driver_data *vc7 = iod->vc7; in vc7_iod_recalc_rate()
966 err = vc7_read_iod(vc7, iod->num); in vc7_iod_recalc_rate()
968 dev_err(&vc7->client->dev, "error reading registers for %s\n", in vc7_iod_recalc_rate()
973 iod_rate = div64_u64(parent_rate, iod->iod_int); in vc7_iod_recalc_rate()
975 pr_debug("%s - %s: iod_int: %u\n", __func__, clk_hw_get_name(hw), iod->iod_int); in vc7_iod_recalc_rate()
976 pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), iod_rate); in vc7_iod_recalc_rate()
986 pr_debug("%s - %s: requested rate: %lu, parent_rate: %lu\n", in vc7_iod_round_rate()
989 vc7_calc_iod_divider(rate, *parent_rate, &iod->iod_int); in vc7_iod_round_rate()
990 iod_rate = div64_u64(*parent_rate, iod->iod_int); in vc7_iod_round_rate()
992 pr_debug("%s - %s: iod_int: %u\n", __func__, clk_hw_get_name(hw), iod->iod_int); in vc7_iod_round_rate()
993 pr_debug("%s - %s rate: %ld\n", __func__, clk_hw_get_name(hw), iod_rate); in vc7_iod_round_rate()
1001 struct vc7_driver_data *vc7 = iod->vc7; in vc7_iod_set_rate()
1004 pr_debug("%s - %s: rate: %lu, parent_rate: %lu\n", in vc7_iod_set_rate()
1008 dev_err(&vc7->client->dev, in vc7_iod_set_rate()
1011 return -EINVAL; in vc7_iod_set_rate()
1014 vc7_write_iod(vc7, iod->num); in vc7_iod_set_rate()
1016 iod_rate = div64_u64(parent_rate, iod->iod_int); in vc7_iod_set_rate()
1018 pr_debug("%s - %s: iod_int: %u\n", __func__, clk_hw_get_name(hw), iod->iod_int); in vc7_iod_set_rate()
1019 pr_debug("%s - %s rate: %ld\n", __func__, clk_hw_get_name(hw), iod_rate); in vc7_iod_set_rate()
1033 struct vc7_driver_data *vc7 = out->vc7; in vc7_clk_out_prepare()
1036 out->out_dis = 0; in vc7_clk_out_prepare()
1038 err = vc7_write_output(vc7, out->num); in vc7_clk_out_prepare()
1040 dev_err(&vc7->client->dev, "error writing registers for %s\n", in vc7_clk_out_prepare()
1045 pr_debug("%s - %s: clk prepared\n", __func__, clk_hw_get_name(hw)); in vc7_clk_out_prepare()
1053 struct vc7_driver_data *vc7 = out->vc7; in vc7_clk_out_unprepare()
1056 out->out_dis = 1; in vc7_clk_out_unprepare()
1058 err = vc7_write_output(vc7, out->num); in vc7_clk_out_unprepare()
1060 dev_err(&vc7->client->dev, "error writing registers for %s\n", in vc7_clk_out_unprepare()
1065 pr_debug("%s - %s: clk unprepared\n", __func__, clk_hw_get_name(hw)); in vc7_clk_out_unprepare()
1071 struct vc7_driver_data *vc7 = out->vc7; in vc7_clk_out_is_enabled()
1074 err = vc7_read_output(vc7, out->num); in vc7_clk_out_is_enabled()
1076 dev_err(&vc7->client->dev, "error reading registers for %s\n", in vc7_clk_out_is_enabled()
1081 is_enabled = !out->out_dis; in vc7_clk_out_is_enabled()
1083 pr_debug("%s - %s: is_enabled=%d\n", __func__, clk_hw_get_name(hw), is_enabled); in vc7_clk_out_is_enabled()
1105 vc7 = devm_kzalloc(&client->dev, sizeof(*vc7), GFP_KERNEL); in vc7_probe()
1107 return -ENOMEM; in vc7_probe()
1110 vc7->client = client; in vc7_probe()
1111 vc7->chip_info = i2c_get_match_data(client); in vc7_probe()
1113 vc7->pin_xin = devm_clk_get(&client->dev, "xin"); in vc7_probe()
1114 if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) { in vc7_probe()
1115 return dev_err_probe(&client->dev, -EPROBE_DEFER, in vc7_probe()
1119 vc7->regmap = devm_regmap_init_i2c(client, &vc7_regmap_config); in vc7_probe()
1120 if (IS_ERR(vc7->regmap)) { in vc7_probe()
1121 return dev_err_probe(&client->dev, PTR_ERR(vc7->regmap), in vc7_probe()
1125 if (of_property_read_string(client->dev.of_node, "clock-output-names", in vc7_probe()
1127 node_name = client->dev.of_node->name; in vc7_probe()
1132 vc7->clk_apll.clk = clk_register_fixed_rate(&client->dev, apll_name, in vc7_probe()
1133 __clk_get_name(vc7->pin_xin), in vc7_probe()
1136 if (IS_ERR(vc7->clk_apll.clk)) { in vc7_probe()
1137 return dev_err_probe(&client->dev, PTR_ERR(vc7->clk_apll.clk), in vc7_probe()
1147 parent_names[0] = __clk_get_name(vc7->clk_apll.clk); in vc7_probe()
1149 vc7->clk_fod[i].num = i; in vc7_probe()
1150 vc7->clk_fod[i].vc7 = vc7; in vc7_probe()
1151 vc7->clk_fod[i].hw.init = &clk_init; in vc7_probe()
1152 ret = devm_clk_hw_register(&client->dev, &vc7->clk_fod[i].hw); in vc7_probe()
1164 parent_names[0] = __clk_get_name(vc7->clk_apll.clk); in vc7_probe()
1166 vc7->clk_iod[i].num = i; in vc7_probe()
1167 vc7->clk_iod[i].vc7 = vc7; in vc7_probe()
1168 vc7->clk_iod[i].hw.init = &clk_init; in vc7_probe()
1169 ret = devm_clk_hw_register(&client->dev, &vc7->clk_iod[i].hw); in vc7_probe()
1176 for (i = 0; i < vc7->chip_info->num_outputs; i++) { in vc7_probe()
1177 out_num = vc7_map_index_to_output(vc7->chip_info->model, i); in vc7_probe()
1186 regmap_read(vc7->regmap, VC7_REG_OUT_BANK_CNFG(bank_idx), &val); in vc7_probe()
1192 dev_err_probe(&client->dev, ret, in vc7_probe()
1199 parent_names[0] = clk_hw_get_name(&bank_src_map.src.fod->hw); in vc7_probe()
1202 parent_names[0] = clk_hw_get_name(&bank_src_map.src.iod->hw); in vc7_probe()
1212 vc7->clk_out[i].num = i; in vc7_probe()
1213 vc7->clk_out[i].vc7 = vc7; in vc7_probe()
1214 vc7->clk_out[i].hw.init = &clk_init; in vc7_probe()
1215 ret = devm_clk_hw_register(&client->dev, &vc7->clk_out[i].hw); in vc7_probe()
1221 ret = of_clk_add_hw_provider(client->dev.of_node, vc7_of_clk_get, vc7); in vc7_probe()
1223 dev_err_probe(&client->dev, ret, "unable to add clk provider\n"); in vc7_probe()
1230 dev_err_probe(&client->dev, ret, in vc7_probe()
1234 clk_unregister_fixed_rate(vc7->clk_apll.clk); in vc7_probe()
1242 of_clk_del_provider(client->dev.of_node); in vc7_remove()
1243 clk_unregister_fixed_rate(vc7->clk_apll.clk); in vc7_remove()
1246 static bool vc7_volatile_reg(struct device *dev, unsigned int reg) in vc7_volatile_reg() argument
1248 if (reg == VC7_PAGE_ADDR) in vc7_volatile_reg()